220 static u32 get_reg(struct udevice *dev, u32 reg)  in get_reg()  argument
222 	struct dp_tx *dp_tx = dev_get_priv(dev);  in get_reg()
227 	res = axi_read(dev->parent, dp_tx->base + reg, &value, AXI_SIZE_32);  in get_reg()
240 static void set_reg(struct udevice *dev, u32 reg, u32 value)  in set_reg()  argument
242 	struct dp_tx *dp_tx = dev_get_priv(dev);  in set_reg()
244 	axi_write(dev->parent, dp_tx->base + reg, &value, AXI_SIZE_32);  in set_reg()
256 static bool is_connected(struct udevice *dev)  in is_connected()  argument
261 		int status = get_reg(dev, REG_INTERRUPT_SIG_STATE) &  in is_connected()
280 static int wait_phy_ready(struct udevice *dev, u32 mask)  in wait_phy_ready()  argument
287 		phy_status = get_reg(dev, REG_PHY_STATUS) & mask;  in wait_phy_ready()
307 static int aux_wait_ready(struct udevice *dev)  in aux_wait_ready()  argument
314 		status = get_reg(dev, REG_INTERRUPT_SIG_STATE);  in aux_wait_ready()
334 static int aux_wait_reply(struct udevice *dev)  in aux_wait_reply()  argument
339 		int status = get_reg(dev, REG_REPLY_STATUS);  in aux_wait_reply()
374 static int aux_request_send(struct udevice *dev,  in aux_request_send()  argument
384 		status = get_reg(dev, REG_REPLY_STATUS);  in aux_request_send()
393 	set_reg(dev, REG_AUX_ADDRESS, request->address);  in aux_request_send()
400 			set_reg(dev,  in aux_request_send()
406 	set_reg(dev, REG_AUX_CMD,  in aux_request_send()
412 	status = aux_wait_reply(dev);  in aux_request_send()
418 	status = get_reg(dev, REG_AUX_REPLY_CODE);  in aux_request_send()
437 			status = get_reg(dev, REG_REPLY_DATA_COUNT);  in aux_request_send()
447 			request->data[index] = get_reg(dev, REG_AUX_REPLY_DATA);  in aux_request_send()
465 static int aux_request(struct udevice *dev, struct aux_transaction *request)  in aux_request()  argument
472 		int status = aux_wait_ready(dev);  in aux_request()
480 		status = aux_request_send(dev, request);  in aux_request()
517 static int aux_common(struct udevice *dev, u32 cmd_type, u32 address,  in aux_common()  argument
561 		status = aux_request(dev, &request);  in aux_common()
583 static int aux_read(struct udevice *dev, u32 dpcd_address, u32 bytes_to_read,  in aux_read()  argument
588 	if (!is_connected(dev))  in aux_read()
592 	status = aux_common(dev, AUX_CMD_READ, dpcd_address,  in aux_read()
612 static int aux_write(struct udevice *dev, u32 dpcd_address, u32 bytes_to_write,  in aux_write()  argument
617 	if (!is_connected(dev))  in aux_write()
621 	status = aux_common(dev, AUX_CMD_WRITE, dpcd_address,  in aux_write()
635 static int initialize(struct udevice *dev)  in initialize()  argument
637 	struct dp_tx *dp_tx = dev_get_priv(dev);  in initialize()
643 	phy_config = get_reg(dev, REG_PHY_CONFIG);  in initialize()
644 	set_reg(dev, REG_PHY_CONFIG, phy_config | PHY_CONFIG_GT_ALL_RESET_MASK);  in initialize()
647 	set_reg(dev, REG_SOFT_RESET,  in initialize()
652 	set_reg(dev, REG_ENABLE, 0);  in initialize()
655 	val = get_reg(dev, REG_AUX_CLK_DIVIDER);  in initialize()
658 	set_reg(dev, REG_AUX_CLK_DIVIDER, val);  in initialize()
661 	set_reg(dev, REG_PHY_CLOCK_SELECT, PHY_CLOCK_SELECT_DEFAULT);  in initialize()
664 	set_reg(dev, REG_PHY_CONFIG,  in initialize()
668 	set_reg(dev, REG_ENABLE, 1);  in initialize()
671 	set_reg(dev, REG_INTERRUPT_MASK,  in initialize()
678 		set_reg(dev, REG_PHY_PRECURSOR_LANE_0 + 4 * k, 0);  in initialize()
681 		set_reg(dev, REG_PHY_VOLTAGE_DIFF_LANE_0 + 4 * k, 0);  in initialize()
684 		set_reg(dev, REG_PHY_POSTCURSOR_LANE_0 + 4 * k, 0);  in initialize()
697 static bool is_link_rate_valid(struct udevice *dev, u8 link_rate)  in is_link_rate_valid()  argument
699 	struct dp_tx *dp_tx = dev_get_priv(dev);  in is_link_rate_valid()
719 static bool is_lane_count_valid(struct udevice *dev, u8 lane_count)  in is_lane_count_valid()  argument
721 	struct dp_tx *dp_tx = dev_get_priv(dev);  in is_lane_count_valid()
742 static int get_rx_capabilities(struct udevice *dev)  in get_rx_capabilities()  argument
744 	struct dp_tx *dp_tx = dev_get_priv(dev);  in get_rx_capabilities()
749 	if (!is_connected(dev))  in get_rx_capabilities()
752 	status = aux_read(dev, DPCD_RECEIVER_CAP_FIELD_START, 16,  in get_rx_capabilities()
764 	if (!is_link_rate_valid(dev, rx_max_link_rate))  in get_rx_capabilities()
770 	if (!is_lane_count_valid(dev, rx_max_lane_count))  in get_rx_capabilities()
784 static void enable_main_link(struct udevice *dev)  in enable_main_link()  argument
787 	set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1);  in enable_main_link()
790 	set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x1);  in enable_main_link()
797 static void disable_main_link(struct udevice *dev)  in disable_main_link()  argument
800 	set_reg(dev, REG_FORCE_SCRAMBLER_RESET, 0x1);  in disable_main_link()
803 	set_reg(dev, REG_ENABLE_MAIN_STREAM, 0x0);  in disable_main_link()
812 static void reset_dp_phy(struct udevice *dev, u32 reset)  in reset_dp_phy()  argument
814 	struct dp_tx *dp_tx = dev_get_priv(dev);  in reset_dp_phy()
817 	set_reg(dev, REG_ENABLE, 0x0);  in reset_dp_phy()
819 	val = get_reg(dev, REG_PHY_CONFIG);  in reset_dp_phy()
822 	set_reg(dev, REG_PHY_CONFIG, val | reset);  in reset_dp_phy()
825 	set_reg(dev, REG_PHY_CONFIG, val);  in reset_dp_phy()
828 	wait_phy_ready(dev, phy_status_lanes_ready_mask(dp_tx->max_lane_count));  in reset_dp_phy()
830 	set_reg(dev, REG_ENABLE, 0x1);  in reset_dp_phy()
845 static int set_enhanced_frame_mode(struct udevice *dev, u8 enable)  in set_enhanced_frame_mode()  argument
847 	struct dp_tx *dp_tx = dev_get_priv(dev);  in set_enhanced_frame_mode()
851 	if (!is_connected(dev))  in set_enhanced_frame_mode()
860 	set_reg(dev, REG_ENHANCED_FRAME_EN,  in set_enhanced_frame_mode()
864 	status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val);  in set_enhanced_frame_mode()
873 	status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val);  in set_enhanced_frame_mode()
890 static int set_lane_count(struct udevice *dev, u8 lane_count)  in set_lane_count()  argument
892 	struct dp_tx *dp_tx = dev_get_priv(dev);  in set_lane_count()
896 	if (!is_connected(dev))  in set_lane_count()
904 	set_reg(dev, REG_LANE_COUNT_SET, dp_tx->link_config.lane_count);  in set_lane_count()
907 	status = aux_read(dev, DPCD_LANE_COUNT_SET, 0x1, &val);  in set_lane_count()
913 	status = aux_write(dev, DPCD_LANE_COUNT_SET, 0x1, &val);  in set_lane_count()
930 static int set_clk_speed(struct udevice *dev, u32 speed)  in set_clk_speed()  argument
932 	struct dp_tx *dp_tx = dev_get_priv(dev);  in set_clk_speed()
938 	val = get_reg(dev, REG_ENABLE);  in set_clk_speed()
939 	set_reg(dev, REG_ENABLE, 0x0);  in set_clk_speed()
942 	set_reg(dev, REG_PHY_CLOCK_SELECT, speed);  in set_clk_speed()
946 		set_reg(dev, REG_ENABLE, 0x1);  in set_clk_speed()
950 	status = wait_phy_ready(dev, mask);  in set_clk_speed()
967 static int set_link_rate(struct udevice *dev, u8 link_rate)  in set_link_rate()  argument
969 	struct dp_tx *dp_tx = dev_get_priv(dev);  in set_link_rate()
976 		status = set_clk_speed(dev, PHY_CLOCK_SELECT_162GBPS);  in set_link_rate()
980 		status = set_clk_speed(dev, PHY_CLOCK_SELECT_270GBPS);  in set_link_rate()
984 		status = set_clk_speed(dev, PHY_CLOCK_SELECT_540GBPS);  in set_link_rate()
995 	set_reg(dev, REG_LINK_BW_SET, dp_tx->link_config.link_rate);  in set_link_rate()
998 	status = aux_write(dev, DPCD_LINK_BW_SET, 1,  in set_link_rate()
1019 static int get_training_delay(struct udevice *dev, int training_state)  in get_training_delay()  argument
1021 	struct dp_tx *dp_tx = dev_get_priv(dev);  in get_training_delay()
1062 static void set_vswing_preemp(struct udevice *dev, u8 *aux_data)  in set_vswing_preemp()  argument
1064 	struct dp_tx *dp_tx = dev_get_priv(dev);  in set_vswing_preemp()
1091 static int adj_vswing_preemp(struct udevice *dev)  in adj_vswing_preemp()  argument
1093 	struct dp_tx *dp_tx = dev_get_priv(dev);  in adj_vswing_preemp()
1156 	set_vswing_preemp(dev, aux_data);  in adj_vswing_preemp()
1161 	status = aux_write(dev, DPCD_TRAINING_LANE0_SET, 4, aux_data);  in adj_vswing_preemp()
1179 static int get_lane_status_adj_reqs(struct udevice *dev)  in get_lane_status_adj_reqs()  argument
1181 	struct dp_tx *dp_tx = dev_get_priv(dev);  in get_lane_status_adj_reqs()
1188 	status = aux_read(dev, DPCD_STATUS_LANE_0_1, 6,  in get_lane_status_adj_reqs()
1209 static int check_clock_recovery(struct udevice *dev, u8 lane_count)  in check_clock_recovery()  argument
1211 	struct dp_tx *dp_tx = dev_get_priv(dev);  in check_clock_recovery()
1254 static int check_channel_equalization(struct udevice *dev, u8 lane_count)  in check_channel_equalization()  argument
1256 	struct dp_tx *dp_tx = dev_get_priv(dev);  in check_channel_equalization()
1319 static int set_training_pattern(struct udevice *dev, u32 pattern)  in set_training_pattern()  argument
1321 	struct dp_tx *dp_tx = dev_get_priv(dev);  in set_training_pattern()
1326 	set_reg(dev, REG_TRAINING_PATTERN_SET, pattern);  in set_training_pattern()
1333 		set_reg(dev, REG_SCRAMBLING_DISABLE, 0);  in set_training_pattern()
1340 		set_reg(dev, REG_SCRAMBLING_DISABLE, 1);  in set_training_pattern()
1351 	set_vswing_preemp(dev, &aux_data[1]);  in set_training_pattern()
1357 		status = aux_write(dev, DPCD_TP_SET, 1, aux_data);  in set_training_pattern()
1359 		status = aux_write(dev, DPCD_TP_SET, 5, aux_data);  in set_training_pattern()
1395 static unsigned int training_state_clock_recovery(struct udevice *dev)  in training_state_clock_recovery()  argument
1397 	struct dp_tx *dp_tx = dev_get_priv(dev);  in training_state_clock_recovery()
1407 	delay_us = get_training_delay(dev, TS_CLOCK_RECOVERY);  in training_state_clock_recovery()
1416 	status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP1);  in training_state_clock_recovery()
1425 		status = get_lane_status_adj_reqs(dev);  in training_state_clock_recovery()
1433 		status = check_clock_recovery(dev,  in training_state_clock_recovery()
1456 		status = adj_vswing_preemp(dev);  in training_state_clock_recovery()
1495 static int training_state_channel_equalization(struct udevice *dev)  in training_state_channel_equalization()  argument
1497 	struct dp_tx *dp_tx = dev_get_priv(dev);  in training_state_channel_equalization()
1506 	delay_us = get_training_delay(dev, TS_CHANNEL_EQUALIZATION);  in training_state_channel_equalization()
1513 		status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP3);  in training_state_channel_equalization()
1515 		status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP2);  in training_state_channel_equalization()
1525 		status = get_lane_status_adj_reqs(dev);  in training_state_channel_equalization()
1531 		status = check_clock_recovery(dev,  in training_state_channel_equalization()
1541 		    check_channel_equalization(dev,  in training_state_channel_equalization()
1547 		status = adj_vswing_preemp(dev);  in training_state_channel_equalization()
1574 static int training_state_adjust_link_rate(struct udevice *dev)  in training_state_adjust_link_rate()  argument
1576 	struct dp_tx *dp_tx = dev_get_priv(dev);  in training_state_adjust_link_rate()
1581 		status = set_link_rate(dev, LINK_BW_SET_270GBPS);  in training_state_adjust_link_rate()
1589 		status = set_link_rate(dev, LINK_BW_SET_162GBPS);  in training_state_adjust_link_rate()
1620 static int trainig_state_adjust_lane_count(struct udevice *dev)  in trainig_state_adjust_lane_count()  argument
1622 	struct dp_tx *dp_tx = dev_get_priv(dev);  in trainig_state_adjust_lane_count()
1627 		status = set_lane_count(dev, LANE_COUNT_SET_2);  in trainig_state_adjust_lane_count()
1633 		status = set_link_rate(dev, dp_tx->link_config.max_link_rate);  in trainig_state_adjust_lane_count()
1641 		status = set_lane_count(dev, LANE_COUNT_SET_1);  in trainig_state_adjust_lane_count()
1647 		status = set_link_rate(dev, dp_tx->link_config.max_link_rate);  in trainig_state_adjust_lane_count()
1677 static int check_link_status(struct udevice *dev, u8 lane_count)  in check_link_status()  argument
1681 	if (!is_connected(dev))  in check_link_status()
1689 		status = get_lane_status_adj_reqs(dev);  in check_link_status()
1694 		if ((check_clock_recovery(dev, lane_count) == 0) &&  in check_link_status()
1695 		    (check_channel_equalization(dev, lane_count) == 0))  in check_link_status()
1726 static int run_training(struct udevice *dev)  in run_training()  argument
1728 	struct dp_tx *dp_tx = dev_get_priv(dev);  in run_training()
1736 				training_state_clock_recovery(dev);  in run_training()
1740 				training_state_channel_equalization(dev);  in run_training()
1744 				training_state_adjust_link_rate(dev);  in run_training()
1748 				trainig_state_adjust_lane_count(dev);  in run_training()
1764 			status = set_training_pattern(dev,  in run_training()
1772 	status = check_link_status(dev, dp_tx->link_config.lane_count);  in run_training()
1790 static int cfg_main_link_max(struct udevice *dev)  in cfg_main_link_max()  argument
1792 	struct dp_tx *dp_tx = dev_get_priv(dev);  in cfg_main_link_max()
1795 	if (!is_connected(dev))  in cfg_main_link_max()
1802 	status = set_link_rate(dev, dp_tx->link_config.max_link_rate);  in cfg_main_link_max()
1810 	status = set_lane_count(dev, dp_tx->link_config.max_lane_count);  in cfg_main_link_max()
1826 static int establish_link(struct udevice *dev)  in establish_link()  argument
1828 	struct dp_tx *dp_tx = dev_get_priv(dev);  in establish_link()
1833 	reset_dp_phy(dev, PHY_CONFIG_PHY_RESET_MASK);  in establish_link()
1836 	disable_main_link(dev);  in establish_link()
1840 	status = wait_phy_ready(dev, mask);  in establish_link()
1845 	status = run_training(dev);  in establish_link()
1848 	status2 = set_training_pattern(dev, TRAINING_PATTERN_SET_OFF);  in establish_link()
1886 static void cfg_msa_recalculate(struct udevice *dev)  in cfg_msa_recalculate()  argument
1888 	struct dp_tx *dp_tx = dev_get_priv(dev);  in cfg_msa_recalculate()
2005 static void set_line_reset(struct udevice *dev)  in set_line_reset()  argument
2007 	struct dp_tx *dp_tx = dev_get_priv(dev);  in set_line_reset()
2022 	reg_val = get_reg(dev, REG_LINE_RESET_DISABLE);  in set_line_reset()
2029 	set_reg(dev, REG_LINE_RESET_DISABLE, reg_val);  in set_line_reset()
2038 static void clear_msa_values(struct udevice *dev)  in clear_msa_values()  argument
2040 	set_reg(dev, REG_MAIN_STREAM_HTOTAL, 0);  in clear_msa_values()
2041 	set_reg(dev, REG_MAIN_STREAM_VTOTAL, 0);  in clear_msa_values()
2042 	set_reg(dev, REG_MAIN_STREAM_POLARITY, 0);  in clear_msa_values()
2043 	set_reg(dev, REG_MAIN_STREAM_HSWIDTH, 0);  in clear_msa_values()
2044 	set_reg(dev, REG_MAIN_STREAM_VSWIDTH, 0);  in clear_msa_values()
2045 	set_reg(dev, REG_MAIN_STREAM_HRES, 0);  in clear_msa_values()
2046 	set_reg(dev, REG_MAIN_STREAM_VRES, 0);  in clear_msa_values()
2047 	set_reg(dev, REG_MAIN_STREAM_HSTART, 0);  in clear_msa_values()
2048 	set_reg(dev, REG_MAIN_STREAM_VSTART, 0);  in clear_msa_values()
2049 	set_reg(dev, REG_MAIN_STREAM_MISC0, 0);  in clear_msa_values()
2050 	set_reg(dev, REG_MAIN_STREAM_MISC1, 0);  in clear_msa_values()
2051 	set_reg(dev, REG_USER_PIXEL_WIDTH, 0);  in clear_msa_values()
2052 	set_reg(dev, REG_USER_DATA_COUNT_PER_LANE, 0);  in clear_msa_values()
2053 	set_reg(dev, REG_M_VID, 0);  in clear_msa_values()
2054 	set_reg(dev, REG_N_VID, 0);  in clear_msa_values()
2056 	set_reg(dev, REG_STREAM1, 0);  in clear_msa_values()
2057 	set_reg(dev, REG_TU_SIZE, 0);  in clear_msa_values()
2058 	set_reg(dev, REG_MIN_BYTES_PER_TU, 0);  in clear_msa_values()
2059 	set_reg(dev, REG_FRAC_BYTES_PER_TU, 0);  in clear_msa_values()
2060 	set_reg(dev, REG_INIT_WAIT, 0);  in clear_msa_values()
2071 static void set_msa_values(struct udevice *dev)  in set_msa_values()  argument
2073 	struct dp_tx *dp_tx = dev_get_priv(dev);  in set_msa_values()
2080 	set_reg(dev, REG_MAIN_STREAM_HTOTAL, msa_config->h_total);  in set_msa_values()
2081 	set_reg(dev, REG_MAIN_STREAM_VTOTAL, msa_config->v_total);  in set_msa_values()
2082 	set_reg(dev, REG_MAIN_STREAM_POLARITY,  in set_msa_values()
2086 	set_reg(dev, REG_MAIN_STREAM_HSWIDTH, msa_config->h_sync_width);  in set_msa_values()
2087 	set_reg(dev, REG_MAIN_STREAM_VSWIDTH, msa_config->v_sync_width);  in set_msa_values()
2088 	set_reg(dev, REG_MAIN_STREAM_HRES, msa_config->h_active);  in set_msa_values()
2089 	set_reg(dev, REG_MAIN_STREAM_VRES, msa_config->v_active);  in set_msa_values()
2090 	set_reg(dev, REG_MAIN_STREAM_HSTART, msa_config->h_start);  in set_msa_values()
2091 	set_reg(dev, REG_MAIN_STREAM_VSTART, msa_config->v_start);  in set_msa_values()
2092 	set_reg(dev, REG_MAIN_STREAM_MISC0, msa_config->misc_0);  in set_msa_values()
2093 	set_reg(dev, REG_MAIN_STREAM_MISC1, msa_config->misc_1);  in set_msa_values()
2094 	set_reg(dev, REG_USER_PIXEL_WIDTH, msa_config->user_pixel_width);  in set_msa_values()
2096 	set_reg(dev, REG_M_VID, msa_config->pixel_clock_hz / 1000);  in set_msa_values()
2097 	set_reg(dev, REG_N_VID, msa_config->n_vid);  in set_msa_values()
2098 	set_reg(dev, REG_USER_DATA_COUNT_PER_LANE, msa_config->data_per_lane);  in set_msa_values()
2100 	set_line_reset(dev);  in set_msa_values()
2102 	set_reg(dev, REG_TU_SIZE, msa_config->transfer_unit_size);  in set_msa_values()
2103 	set_reg(dev, REG_MIN_BYTES_PER_TU, msa_config->avg_bytes_per_tu / 1000);  in set_msa_values()
2104 	set_reg(dev, REG_FRAC_BYTES_PER_TU,  in set_msa_values()
2106 	set_reg(dev, REG_INIT_WAIT, msa_config->init_wait);  in set_msa_values()
2118 static void logicore_dp_tx_set_msa(struct udevice *dev,  in logicore_dp_tx_set_msa()  argument
2121 	struct dp_tx *dp_tx = dev_get_priv(dev);  in logicore_dp_tx_set_msa()
2151 static int logicore_dp_tx_video_enable(struct udevice *dev,  in logicore_dp_tx_video_enable()  argument
2154 	struct dp_tx *dp_tx = dev_get_priv(dev);  in logicore_dp_tx_video_enable()
2158 	if (!is_connected(dev)) {  in logicore_dp_tx_video_enable()
2163 	initialize(dev);  in logicore_dp_tx_video_enable()
2165 	disable_main_link(dev);  in logicore_dp_tx_video_enable()
2167 	logicore_dp_tx_set_msa(dev, msa);  in logicore_dp_tx_video_enable()
2169 	get_rx_capabilities(dev);  in logicore_dp_tx_video_enable()
2172 	aux_write(dev, DPCD_SET_POWER_DP_PWR_VOLTAGE, 1, &power);  in logicore_dp_tx_video_enable()
2173 	set_enhanced_frame_mode(dev, true);  in logicore_dp_tx_video_enable()
2174 	cfg_main_link_max(dev);  in logicore_dp_tx_video_enable()
2175 	res = establish_link(dev);  in logicore_dp_tx_video_enable()
2180 	cfg_msa_recalculate(dev);  in logicore_dp_tx_video_enable()
2182 	clear_msa_values(dev);  in logicore_dp_tx_video_enable()
2183 	set_msa_values(dev);  in logicore_dp_tx_video_enable()
2185 	enable_main_link(dev);  in logicore_dp_tx_video_enable()
2194 static int logicore_dp_tx_enable(struct udevice *dev, int panel_bpp,  in logicore_dp_tx_enable()  argument
2257 	if (clk_get_by_index(dev, 0, &pixclock)) {  in logicore_dp_tx_enable()
2258 		printf("%s: Could not get pixelclock\n", dev->name);  in logicore_dp_tx_enable()
2263 	return logicore_dp_tx_video_enable(dev, msa);  in logicore_dp_tx_enable()
2266 static int logicore_dp_tx_probe(struct udevice *dev)  in logicore_dp_tx_probe()  argument
2268 	struct dp_tx *dp_tx = dev_get_priv(dev);  in logicore_dp_tx_probe()
2275 	dp_tx->base = dev_read_u32_default(dev, "reg", -1);  in logicore_dp_tx_probe()