Lines Matching full:default

23 /* Default AXI clock frequency value */
26 /* Default DP phy clock value */
680 		/* Write default voltage swing levels to the TX registers. */  in initialize()
683 		/* Write default pre-emphasis levels to the TX registers. */  in initialize()
986 	default:  in set_link_rate()
1045 	default:  in get_training_delay()
1046 		/* Default to 20 ms. */  in get_training_delay()
1229 	default:  in check_clock_recovery()
1274 	default:  in check_channel_equalization()
1294 	default:  in check_channel_equalization()
1343 	default:  in set_training_pattern()
1596 	default:  in training_state_adjust_link_rate()
1654 	default:  in trainig_state_adjust_lane_count()
1750 		default:  in run_training()