Lines Matching full:displayport

5  * Driver for XILINX LogiCore DisplayPort v6.1 TX (Source)
79 * by the DisplayPort 1.2 specification
81 * by the DisplayPort 1.2 specification
273 * wait_phy_ready() - Wait for the DisplayPort PHY to come out of reset
312 /* Wait until the DisplayPort TX core is ready. */ in aux_wait_ready()
368 * for write commands), and the data size to the DisplayPort TX core.
398 /* Feed write data into the DisplayPort TX core's write FIFO. */ in aux_request_send()
459 * channel. If waiting for a reply times out, or if the DisplayPort TX core
577 * device's DisplayPort Configuration data (DPCD) address space. The read
606 * the RX device's DisplayPort Configuration data (DPCD) address space. The
651 /* disable the DisplayPort TX core. */ in initialize()
660 /* set the DisplayPort TX core's clock speed. */ in initialize()
667 /* enable the DisplayPort TX core. */ in initialize()
840 * both the DisplayPort TX core and the RX device.
859 /* Write enhanced frame mode enable to the DisplayPort TX core. */ in set_enhanced_frame_mode()
886 * the DisplayPort TX core and the RX device.
903 /* Write the new lane count to the DisplayPort TX core. */ in set_lane_count()
925 * Set the clock frequency for the DisplayPort PHY corresponding to a desired
937 /* Disable the DisplayPort TX core first. */ in set_clk_speed()
944 /* Re-enable the DisplayPort TX core if it was previously enabled. */ in set_clk_speed()
962 * Set the data rate to be used by the main link for both the DisplayPort TX
972 /* Write a corresponding clock frequency to the DisplayPort TX core. */ in set_link_rate()
994 /* Write new link rate to the DisplayPort TX core. */ in set_link_rate()
1137 * DisplayPort v1.2 Specification, section 3.1.5.2. in adj_vswing_preemp()
1153 * Make the adjustments to both the DisplayPort TX core and the RX in adj_vswing_preemp()
1201 * Check if the RX device's DisplayPort Configuration data (DPCD) indicates
1246 * Check if the RX device's DisplayPort Configuration data (DPCD) indicates
1315 * DisplayPort TX core and the RX device.
1325 /* Write to the DisplayPort TX core. */ in set_training_pattern()
1330 /* Write scrambler disable to the DisplayPort TX core. */ in set_training_pattern()
1348 * Make the adjustments to both the DisplayPort TX core and the RX in set_training_pattern()
1380 * DisplayPort Configuration data (DPCD) register,
1391 * 3.5.1.2.1 of the DisplayPort 1.2a specification document.
1480 * DisplayPort Configuration data (DPCD) register,
1491 * section 3.5.1.2.2 of the DisplayPort 1.2a specification document.
1671 * Check if the receiver's DisplayPort Configuration data (DPCD) indicates the
1785 * Determine the common capabilities between the DisplayPort TX core and the RX
1800 * DisplayPort TX core and the RX device. in cfg_main_link_max()
1808 * DisplayPort TX core and the RX device. in cfg_main_link_max()
1901 * capabilities of the DisplayPort TX core. in cfg_msa_recalculate()
2036 * Clear the main stream attributes registers of the DisplayPort TX core.
2067 * Set the main stream attributes registers of the DisplayPort TX