Lines Matching +full:0 +full:x00048000
16 #define IPU_DISP0_BASE 0x00000000
19 #define IPU_CM_REG_BASE 0x00000000
20 #define IPU_STAT_REG_BASE 0x00000200
21 #define IPU_IDMAC_REG_BASE 0x00008000
22 #define IPU_ISP_REG_BASE 0x00010000
23 #define IPU_DP_REG_BASE 0x00018000
24 #define IPU_IC_REG_BASE 0x00020000
25 #define IPU_IRT_REG_BASE 0x00028000
26 #define IPU_CSI0_REG_BASE 0x00030000
27 #define IPU_CSI1_REG_BASE 0x00038000
28 #define IPU_DI0_REG_BASE 0x00040000
29 #define IPU_DI1_REG_BASE 0x00048000
30 #define IPU_SMFC_REG_BASE 0x00050000
31 #define IPU_DC_REG_BASE 0x00058000
32 #define IPU_DMFC_REG_BASE 0x00060000
33 #define IPU_VDI_REG_BASE 0x00680000
35 #define IPU_CPMEM_REG_BASE 0x01000000
36 #define IPU_LUT_REG_BASE 0x01020000
37 #define IPU_SRM_REG_BASE 0x01040000
38 #define IPU_TPM_REG_BASE 0x01060000
39 #define IPU_DC_TMPL_REG_BASE 0x01080000
40 #define IPU_ISP_TBPR_REG_BASE 0x010C0000
42 #define IPU_CPMEM_REG_BASE 0x00100000
43 #define IPU_LUT_REG_BASE 0x00120000
44 #define IPU_SRM_REG_BASE 0x00140000
45 #define IPU_TPM_REG_BASE 0x00160000
46 #define IPU_DC_TMPL_REG_BASE 0x00180000
47 #define IPU_ISP_TBPR_REG_BASE 0x001C0000
54 #define DC_EVT_NF 0
64 #define DC_EVT_NEW_ADDR_W_0 0
81 IPU_CONF_DP_EN = 0x00000020,
82 IPU_CONF_DI0_EN = 0x00000040,
83 IPU_CONF_DI1_EN = 0x00000080,
84 IPU_CONF_DMFC_EN = 0x00000400,
85 IPU_CONF_DC_EN = 0x00000200,
87 DI0_COUNTER_RELEASE = 0x01000000,
88 DI1_COUNTER_RELEASE = 0x02000000,
93 DI_GEN_DI_CLK_EXT = 0x100000,
94 DI_GEN_POLARITY_1 = 0x00000001,
95 DI_GEN_POLARITY_2 = 0x00000002,
96 DI_GEN_POLARITY_3 = 0x00000004,
97 DI_GEN_POLARITY_4 = 0x00000008,
98 DI_GEN_POLARITY_5 = 0x00000010,
99 DI_GEN_POLARITY_6 = 0x00000020,
100 DI_GEN_POLARITY_7 = 0x00000040,
101 DI_GEN_POLARITY_8 = 0x00000080,
102 DI_GEN_POL_CLK = 0x20000,
104 DI_POL_DRDY_DATA_POLARITY = 0x00000080,
105 DI_POL_DRDY_POLARITY_15 = 0x00000010,
108 DC_WR_CH_CONF_FIELD_MODE = 0x00000200,
110 DC_WR_CH_CONF_PROG_TYPE_MASK = 0x000000E0,
111 DC_WR_CH_CONF_PROG_DI_ID = 0x00000004,
113 DC_WR_CH_CONF_PROG_DISP_ID_MASK = 0x00000018,
115 DP_COM_CONF_FG_EN = 0x00000001,
116 DP_COM_CONF_GWSEL = 0x00000002,
117 DP_COM_CONF_GWAM = 0x00000004,
118 DP_COM_CONF_GWCKE = 0x00000008,
119 DP_COM_CONF_CSC_DEF_MASK = 0x00000300,
121 DP_COM_CONF_CSC_DEF_FG = 0x00000300,
122 DP_COM_CONF_CSC_DEF_BG = 0x00000200,
123 DP_COM_CONF_CSC_DEF_BOTH = 0x00000100,
124 DP_COM_CONF_GAMMA_EN = 0x00001000,
125 DP_COM_CONF_GAMMA_YUV_EN = 0x00002000,
129 DI_PIN11 = 0,
138 DI_PIN_SER_CLK = 0,
144 DI_SYNC_CLK = 0,
304 #define IPU_FS_PROC_FLOW1 (&IPU_CM_REG->fs_proc_flow[0])
307 #define IPU_FS_DISP_FLOW1 (&IPU_CM_REG->fs_disp_flow[0])
320 #define IPUIRQ_2_MASK(irq) (1UL << ((irq) & 0x1F))
353 #define DMFC_GENERAL1 (&DMFC_REG->general[0])
366 case 0: in dc_ch_offset()
396 #define DP_SYNC 0
397 #define DP_ASYNC0 0x60
398 #define DP_ASYNC1 0xBC
404 #define DP_CSC_A_0() (&DP_REG->csca_sync[0])
409 #define DP_CSC_0() (&DP_REG->csc_sync[0])
413 #define WROD(lf) (0x18 | (lf << 1))