67 			debug("count = 3 payload = %x, %x %x %x\n",  in exynos_mipi_dsi_long_data_wr()
74 			debug("count = 2 payload = %x, %x %x\n", payload,  in exynos_mipi_dsi_long_data_wr()
86 			debug("count = 4 payload = %x, %x %x %x %x\n",  in exynos_mipi_dsi_long_data_wr()
104 		debug("state is ULPS.\n");  in exynos_mipi_dsi_wr_data()
121 				debug("SRF header fifo is not empty.\n");  in exynos_mipi_dsi_wr_data()
135 		debug("data0 = %x data1 = %x\n",  in exynos_mipi_dsi_wr_data()
193 			debug("count = %d payload = %x,%x %x %x\n",  in exynos_mipi_dsi_wr_data()
224 		debug("data id %x is not supported current DSI spec.\n",  in exynos_mipi_dsi_wr_data()
285 		debug("fin_pll range should be 6MHz ~ 12MHz\n");  in exynos_mipi_dsi_change_pll()
303 	debug("dfvco = %lu, dfin_pll = %lu, main_divider = %d\n",  in exynos_mipi_dsi_change_pll()
306 		debug("fvco range should be 500MHz ~ 1000MHz\n");  in exynos_mipi_dsi_change_pll()
309 	debug("dpll_out = %lu, dfvco = %lu, scaler = %d\n",  in exynos_mipi_dsi_change_pll()
319 	debug("freq_band = %d\n", freq_band);  in exynos_mipi_dsi_change_pll()
334 	debug("FOUT of mipi dphy pll is %luMHz\n",  in exynos_mipi_dsi_change_pll()
359 				debug("failed to get hs clock.\n");  in exynos_mipi_dsi_set_clock()
368 			debug("not support EXT CLK source for MIPI DSIM\n");  in exynos_mipi_dsi_set_clock()
370 			debug("not support EXT CLK source for MIPI DSIM\n");  in exynos_mipi_dsi_set_clock()
374 		debug("esc_div = %d, byte_clk = %lu, esc_clk = %lu\n",  in exynos_mipi_dsi_set_clock()
381 		debug("escape_clk = %lu, byte_clk = %lu, esc_div = %d\n",  in exynos_mipi_dsi_set_clock()
393 		debug("byte clock is %luMHz\n",  in exynos_mipi_dsi_set_clock()
395 		debug("escape clock that user's need is %lu\n",  in exynos_mipi_dsi_set_clock()
397 		debug("escape clock divider is %x\n", esc_div);  in exynos_mipi_dsi_set_clock()
398 		debug("escape clock is %luMHz\n",  in exynos_mipi_dsi_set_clock()
404 			debug("error rate is %lu over.\n",  in exynos_mipi_dsi_set_clock()
409 			debug("error rate is %lu under.\n",  in exynos_mipi_dsi_set_clock()
447 		debug("data lane is invalid.\n");  in exynos_mipi_dsi_init_dsim()
512 	debug("lcd panel ==> width = %d, height = %d\n",  in exynos_mipi_dsi_set_display_mode()
539 				debug("DSI Master is not stop state.\n");  in exynos_mipi_dsi_init_link()
540 				debug("Check initialization process\n");  in exynos_mipi_dsi_init_link()
558 		debug("DSI Master is already init.\n");  in exynos_mipi_dsi_init_link()
579 			debug("clock source is external bypass.\n");  in exynos_mipi_dsi_set_hs_enable()
581 		debug("DSIM is not stop state.\n");  in exynos_mipi_dsi_set_hs_enable()
591 			debug("HS Clock lane is not enabled.\n");  in exynos_mipi_dsi_set_data_transfer_mode()
599 			debug("DSI Master is not STOP or HSDT state.\n");  in exynos_mipi_dsi_set_data_transfer_mode()