Lines Matching +full:dp +full:- +full:bridge
1 // SPDX-License-Identifier: GPL-2.0+
21 #include <asm/arch/dp.h>
31 disp_info->h_total = disp_info->h_res + disp_info->h_sync_width + in exynos_dp_disp_info()
32 disp_info->h_back_porch + disp_info->h_front_porch; in exynos_dp_disp_info()
33 disp_info->v_total = disp_info->v_res + disp_info->v_sync_width + in exynos_dp_disp_info()
34 disp_info->v_back_porch + disp_info->v_front_porch; in exynos_dp_disp_info()
79 * into E-EDID in I2C device, 0x30. in exynos_dp_read_edid()
82 /* Read Extension Flag, Number of 128-byte EDID extension blocks */ in exynos_dp_read_edid()
87 printf("DP EDID data includes a single extension!\n"); in exynos_dp_read_edid()
96 printf("DP EDID Read failed!\n"); in exynos_dp_read_edid()
97 return -1; in exynos_dp_read_edid()
101 printf("DP EDID bad checksum!\n"); in exynos_dp_read_edid()
102 return -1; in exynos_dp_read_edid()
112 printf("DP EDID Read failed!\n"); in exynos_dp_read_edid()
113 return -1; in exynos_dp_read_edid()
117 printf("DP EDID bad checksum!\n"); in exynos_dp_read_edid()
118 return -1; in exynos_dp_read_edid()
132 debug("DP EDID data does not include any extensions.\n"); in exynos_dp_read_edid()
142 printf("DP EDID Read failed!\n"); in exynos_dp_read_edid()
143 return -1; in exynos_dp_read_edid()
147 printf("DP EDID bad checksum!\n"); in exynos_dp_read_edid()
148 return -1; in exynos_dp_read_edid()
162 debug("DP EDID Read success!\n"); in exynos_dp_read_edid()
185 /* Read DPCD 0x0000-0x000b */ in exynos_dp_handle_edid()
190 printf("DP read_byte_from_dpcd() failed\n"); in exynos_dp_handle_edid()
193 retry_cnt--; in exynos_dp_handle_edid()
201 priv->dpcd_rev = temp; in exynos_dp_handle_edid()
203 printf("DP Wrong DPCD Rev : %x\n", temp); in exynos_dp_handle_edid()
204 return -ENODEV; in exynos_dp_handle_edid()
209 priv->lane_bw = temp; in exynos_dp_handle_edid()
211 printf("DP Wrong MAX LINK RATE : %x\n", temp); in exynos_dp_handle_edid()
212 return -EINVAL; in exynos_dp_handle_edid()
216 if (priv->dpcd_rev == DP_DPCD_REV_11) { in exynos_dp_handle_edid()
219 priv->dpcd_efc = 1; in exynos_dp_handle_edid()
221 priv->dpcd_efc = 0; in exynos_dp_handle_edid()
224 priv->dpcd_efc = 0; in exynos_dp_handle_edid()
229 priv->lane_cnt = temp; in exynos_dp_handle_edid()
231 printf("DP Wrong MAX LANE COUNT : %x\n", temp); in exynos_dp_handle_edid()
232 return -EINVAL; in exynos_dp_handle_edid()
237 printf("DP exynos_dp_read_edid() failed\n"); in exynos_dp_handle_edid()
238 return -EINVAL; in exynos_dp_handle_edid()
248 * the DP inter pair skew issue for at least 10 us in exynos_dp_init_training()
252 /* All DP analog module power up */ in exynos_dp_init_training()
262 debug("DP: %s was called\n", __func__); in exynos_dp_link_start()
264 priv->lt_info.lt_status = DP_LT_CR; in exynos_dp_link_start()
265 priv->lt_info.ep_loop = 0; in exynos_dp_link_start()
266 priv->lt_info.cr_loop[0] = 0; in exynos_dp_link_start()
267 priv->lt_info.cr_loop[1] = 0; in exynos_dp_link_start()
268 priv->lt_info.cr_loop[2] = 0; in exynos_dp_link_start()
269 priv->lt_info.cr_loop[3] = 0; in exynos_dp_link_start()
275 printf("DP write_dpcd_byte failed\n"); in exynos_dp_link_start()
280 exynos_dp_set_link_bandwidth(regs, priv->lane_bw); in exynos_dp_link_start()
281 exynos_dp_set_lane_count(regs, priv->lane_cnt); in exynos_dp_link_start()
284 buf[0] = priv->lane_bw; in exynos_dp_link_start()
285 buf[1] = priv->lane_cnt; in exynos_dp_link_start()
289 printf("DP write_dpcd_byte failed\n"); in exynos_dp_link_start()
294 priv->lane_cnt); in exynos_dp_link_start()
314 printf("DP write_dpcd_byte failed\n"); in exynos_dp_link_start()
330 printf("DP request_link_training_req failed\n"); in exynos_dp_training_pattern_dis()
331 return -EAGAIN; in exynos_dp_training_pattern_dis()
346 printf("DP read_from_dpcd failed\n"); in exynos_dp_enable_rx_to_enhanced_mode()
347 return -EAGAIN; in exynos_dp_enable_rx_to_enhanced_mode()
357 printf("DP write_to_dpcd failed\n"); in exynos_dp_enable_rx_to_enhanced_mode()
358 return -EAGAIN; in exynos_dp_enable_rx_to_enhanced_mode()
372 printf("DP rx_enhance_mode failed\n"); in exynos_dp_set_enhanced_mode()
373 return -EAGAIN; in exynos_dp_set_enhanced_mode()
398 printf("DP read lane status failed\n"); in exynos_dp_read_dpcd_lane_stat()
402 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_read_dpcd_lane_stat()
406 return -EINVAL; in exynos_dp_read_dpcd_lane_stat()
428 printf("DP read adjust request failed\n"); in exynos_dp_read_dpcd_adj_req()
429 return -EAGAIN; in exynos_dp_read_dpcd_adj_req()
445 printf("DP training_pattern_disable() failed\n"); in exynos_dp_equalizer_err_link()
446 priv->lt_info.lt_status = DP_LT_FAIL; in exynos_dp_equalizer_err_link()
449 ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc); in exynos_dp_equalizer_err_link()
451 printf("DP set_enhanced_mode() failed\n"); in exynos_dp_equalizer_err_link()
452 priv->lt_info.lt_status = DP_LT_FAIL; in exynos_dp_equalizer_err_link()
463 if (priv->lane_bw == DP_LANE_BW_2_70) { in exynos_dp_reduce_link_rate()
464 priv->lane_bw = DP_LANE_BW_1_62; in exynos_dp_reduce_link_rate()
465 printf("DP Change lane bw to 1.62Gbps\n"); in exynos_dp_reduce_link_rate()
466 priv->lt_info.lt_status = DP_LT_START; in exynos_dp_reduce_link_rate()
471 printf("DP training_patter_disable() failed\n"); in exynos_dp_reduce_link_rate()
473 ret = exynos_dp_set_enhanced_mode(regs, priv->dpcd_efc); in exynos_dp_reduce_link_rate()
475 printf("DP set_enhanced_mode() failed\n"); in exynos_dp_reduce_link_rate()
477 priv->lt_info.lt_status = DP_LT_FAIL; in exynos_dp_reduce_link_rate()
494 debug("DP: %s was called\n", __func__); in exynos_dp_process_clock_recovery()
499 printf("DP read lane status failed\n"); in exynos_dp_process_clock_recovery()
500 priv->lt_info.lt_status = DP_LT_FAIL; in exynos_dp_process_clock_recovery()
505 debug("DP clock Recovery training succeed\n"); in exynos_dp_process_clock_recovery()
508 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_process_clock_recovery()
512 priv->lt_info.lt_status = DP_LT_FAIL; in exynos_dp_process_clock_recovery()
537 printf("DP write training pattern1 failed\n"); in exynos_dp_process_clock_recovery()
538 priv->lt_info.lt_status = DP_LT_FAIL; in exynos_dp_process_clock_recovery()
541 priv->lt_info.lt_status = DP_LT_ET; in exynos_dp_process_clock_recovery()
543 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_process_clock_recovery()
549 printf("DP read adj req failed\n"); in exynos_dp_process_clock_recovery()
550 priv->lt_info.lt_status = DP_LT_FAIL; in exynos_dp_process_clock_recovery()
563 priv->lt_info.cr_loop[i]++; in exynos_dp_process_clock_recovery()
564 if (priv->lt_info.cr_loop[i] == MAX_CR_LOOP) in exynos_dp_process_clock_recovery()
584 printf("DP write training pattern2 failed\n"); in exynos_dp_process_clock_recovery()
585 priv->lt_info.lt_status = DP_LT_FAIL; in exynos_dp_process_clock_recovery()
608 printf("DP read lane status failed\n"); in exynos_dp_process_equalizer_training()
609 priv->lt_info.lt_status = DP_LT_FAIL; in exynos_dp_process_equalizer_training()
613 debug("DP lane stat : %x\n", lane_stat); in exynos_dp_process_equalizer_training()
620 priv->lt_info.lt_status = DP_LT_FAIL; in exynos_dp_process_equalizer_training()
627 for (i = 0; i < priv->lane_cnt; i++) { in exynos_dp_process_equalizer_training()
631 printf("DP read adj req 1 failed\n"); in exynos_dp_process_equalizer_training()
632 priv->lt_info.lt_status = DP_LT_FAIL; in exynos_dp_process_equalizer_training()
650 debug("DP Equalizer training succeed\n"); in exynos_dp_process_equalizer_training()
655 debug("DP final BandWidth : %x\n", f_bw); in exynos_dp_process_equalizer_training()
656 debug("DP final Lane Count : %x\n", f_lane_cnt); in exynos_dp_process_equalizer_training()
658 priv->lt_info.lt_status = DP_LT_FINISHED; in exynos_dp_process_equalizer_training()
663 priv->lt_info.ep_loop++; in exynos_dp_process_equalizer_training()
665 if (priv->lt_info.ep_loop > MAX_EQ_LOOP) { in exynos_dp_process_equalizer_training()
666 if (priv->lane_bw == DP_LANE_BW_2_70) { in exynos_dp_process_equalizer_training()
670 priv->lt_info.lt_status = in exynos_dp_process_equalizer_training()
676 for (i = 0; i < priv->lane_cnt; i++) in exynos_dp_process_equalizer_training()
684 printf("DP set lt pattern failed\n"); in exynos_dp_process_equalizer_training()
685 priv->lt_info.lt_status = in exynos_dp_process_equalizer_training()
692 } else if (priv->lane_bw == DP_LANE_BW_2_70) { in exynos_dp_process_equalizer_training()
695 priv->lt_info.lt_status = DP_LT_FAIL; in exynos_dp_process_equalizer_training()
709 if (priv->lane_cnt == 1) in exynos_dp_sw_link_training()
714 priv->lt_info.lt_status = DP_LT_START; in exynos_dp_sw_link_training()
718 switch (priv->lt_info.lt_status) { in exynos_dp_sw_link_training()
722 printf("DP LT:link start failed\n"); in exynos_dp_sw_link_training()
730 printf("DP LT:clock recovery failed\n"); in exynos_dp_sw_link_training()
738 printf("DP LT:equalizer training failed\n"); in exynos_dp_sw_link_training()
746 return -1; in exynos_dp_sw_link_training()
762 printf("DP dp_sw_link_training() failed\n"); in exynos_dp_set_link_train()
796 if (priv->video_info.master_mode) { in exynos_dp_config_video()
797 printf("DP does not support master mode\n"); in exynos_dp_config_video()
798 return -ENODEV; in exynos_dp_config_video()
802 &priv->video_info); in exynos_dp_config_video()
805 exynos_dp_set_video_color_format(regs, &priv->video_info); in exynos_dp_config_video()
807 if (priv->video_info.bist_mode) { in exynos_dp_config_video()
809 return -1; in exynos_dp_config_video()
814 printf("DP PLL is not locked yet\n"); in exynos_dp_config_video()
815 return -EIO; in exynos_dp_config_video()
818 if (priv->video_info.master_mode == 0) { in exynos_dp_config_video()
824 printf("DP stream_clock_on failed\n"); in exynos_dp_config_video()
827 retry_cnt--; in exynos_dp_config_video()
841 if (priv->video_info.bist_pattern != COLOR_RAMP && in exynos_dp_config_video()
842 priv->video_info.bist_pattern != BALCK_WHITE_V_LINES && in exynos_dp_config_video()
843 priv->video_info.bist_pattern != COLOR_SQUARE) in exynos_dp_config_video()
845 priv->video_info.bist_mode); in exynos_dp_config_video()
854 priv->video_info.master_mode); in exynos_dp_config_video()
859 if (priv->video_info.master_mode == 0) { in exynos_dp_config_video()
865 printf("DP Timeout of video stream\n"); in exynos_dp_config_video()
868 retry_cnt--; in exynos_dp_config_video()
881 const void *blob = gd->fdt_blob; in exynos_dp_ofdata_to_platdata()
887 debug("Can't get the DP base address\n"); in exynos_dp_ofdata_to_platdata()
888 return -EINVAL; in exynos_dp_ofdata_to_platdata()
890 priv->regs = (struct exynos_dp *)addr; in exynos_dp_ofdata_to_platdata()
891 priv->disp_info.h_res = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
892 "samsung,h-res", 0); in exynos_dp_ofdata_to_platdata()
893 priv->disp_info.h_sync_width = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
894 "samsung,h-sync-width", 0); in exynos_dp_ofdata_to_platdata()
895 priv->disp_info.h_back_porch = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
896 "samsung,h-back-porch", 0); in exynos_dp_ofdata_to_platdata()
897 priv->disp_info.h_front_porch = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
898 "samsung,h-front-porch", 0); in exynos_dp_ofdata_to_platdata()
899 priv->disp_info.v_res = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
900 "samsung,v-res", 0); in exynos_dp_ofdata_to_platdata()
901 priv->disp_info.v_sync_width = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
902 "samsung,v-sync-width", 0); in exynos_dp_ofdata_to_platdata()
903 priv->disp_info.v_back_porch = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
904 "samsung,v-back-porch", 0); in exynos_dp_ofdata_to_platdata()
905 priv->disp_info.v_front_porch = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
906 "samsung,v-front-porch", 0); in exynos_dp_ofdata_to_platdata()
907 priv->disp_info.v_sync_rate = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
908 "samsung,v-sync-rate", 0); in exynos_dp_ofdata_to_platdata()
910 priv->lt_info.lt_status = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
911 "samsung,lt-status", 0); in exynos_dp_ofdata_to_platdata()
913 priv->video_info.master_mode = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
914 "samsung,master-mode", 0); in exynos_dp_ofdata_to_platdata()
915 priv->video_info.bist_mode = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
916 "samsung,bist-mode", 0); in exynos_dp_ofdata_to_platdata()
917 priv->video_info.bist_pattern = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
918 "samsung,bist-pattern", 0); in exynos_dp_ofdata_to_platdata()
919 priv->video_info.h_sync_polarity = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
920 "samsung,h-sync-polarity", 0); in exynos_dp_ofdata_to_platdata()
921 priv->video_info.v_sync_polarity = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
922 "samsung,v-sync-polarity", 0); in exynos_dp_ofdata_to_platdata()
923 priv->video_info.interlaced = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
925 priv->video_info.color_space = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
926 "samsung,color-space", 0); in exynos_dp_ofdata_to_platdata()
927 priv->video_info.dynamic_range = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
928 "samsung,dynamic-range", 0); in exynos_dp_ofdata_to_platdata()
929 priv->video_info.ycbcr_coeff = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
930 "samsung,ycbcr-coeff", 0); in exynos_dp_ofdata_to_platdata()
931 priv->video_info.color_depth = fdtdec_get_int(blob, node, in exynos_dp_ofdata_to_platdata()
932 "samsung,color-depth", 0); in exynos_dp_ofdata_to_platdata()
945 debug("video bridge init failed: %d\n", ret); in exynos_dp_bridge_init()
950 * We need to wait for 90ms after bringing up the bridge since there in exynos_dp_bridge_init()
952 * high comes within 7ms of de-asserting PD and persists for at least in exynos_dp_bridge_init()
953 * 15ms. The real high comes roughly 50ms after PD is de-asserted. The in exynos_dp_bridge_init()
961 if (!ret || ret == -ENOENT) in exynos_dp_bridge_init()
964 debug("%s: eDP bridge failed to come up; try %d of %d\n", in exynos_dp_bridge_init()
968 /* Immediately go into bridge reset if the hp line is not high */ in exynos_dp_bridge_init()
969 return -EIO; in exynos_dp_bridge_init()
979 /* Configure I2C registers for Parade bridge */ in exynos_dp_bridge_setup()
982 debug("video bridge init failed: %d\n", ret); in exynos_dp_bridge_setup()
986 if (strncmp(dev->driver->name, "parade", 6)) { in exynos_dp_bridge_setup()
995 if (num_tries == max_tries - 1) in exynos_dp_bridge_setup()
999 * If we're here, the bridge chip failed to initialise. in exynos_dp_bridge_setup()
1000 * Power down the bridge in an attempt to reset. in exynos_dp_bridge_setup()
1017 struct exynos_dp *regs = priv->regs; in exynos_dp_enable()
1021 exynos_dp_disp_info(&priv->disp_info); in exynos_dp_enable()
1023 ret = exynos_dp_bridge_setup(gd->fdt_blob); in exynos_dp_enable()
1024 if (ret && ret != -ENODEV) in exynos_dp_enable()
1025 printf("LCD bridge failed to enable: %d\n", ret); in exynos_dp_enable()
1031 printf("DP exynos_dp_init_dp() failed\n"); in exynos_dp_enable()
1043 printf("DP link training fail\n"); in exynos_dp_enable()
1051 exynos_dp_set_link_bandwidth(regs, priv->lane_bw); in exynos_dp_enable()
1052 exynos_dp_set_lane_count(regs, priv->lane_cnt); in exynos_dp_enable()
1057 printf("Exynos DP init failed\n"); in exynos_dp_enable()
1061 debug("Exynos DP init done\n"); in exynos_dp_enable()
1072 { .compatible = "samsung,exynos5-dp" },