Lines Matching +full:pixel +full:- +full:clock +full:- +full:frequency

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Porting to u-boot:
8  * Copyright (C) 2008-2009 MontaVista Software Inc.
9  * Copyright (C) 2008-2009 Texas Instruments Inc
51 	unsigned int	pxl_clk;	/* Pixel clock */
52 	unsigned char	invert_pxl_clk;	/* Invert Pixel clock */
65 	/* AC Bias Pin Frequency */
74 	/* Bits per pixel */
83 	/* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */
86 	/* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */
89 	/* Invert line clock */
92 	/* Invert frame clock  */
101 	/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */