Lines Matching +full:bias +full:- +full:ctrl +full:- +full:value
1 // SPDX-License-Identifier: GPL-2.0+
3 * Porting to u-boot:
8 * Copyright (C) 2008-2009 MontaVista Software Inc.
9 * Copyright (C) 2008-2009 Texas Instruments Inc
26 #include "da8xx-fb.h"
101 u32 ctrl; member
193 .height = -1,
194 .width = -1,
195 .pixclock = 46666, /* 46us - AUO display */
224 &da8xx_fb_reg_base->clk_reset); in lcd_enable_raster()
230 &da8xx_fb_reg_base->clk_reset); in lcd_enable_raster()
234 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); in lcd_enable_raster()
237 &da8xx_fb_reg_base->raster_ctrl); in lcd_enable_raster()
251 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); in lcd_disable_raster()
254 &da8xx_fb_reg_base->raster_ctrl); in lcd_disable_raster()
259 stat = lcdc_read(&da8xx_fb_reg_base->stat); in lcd_disable_raster()
261 stat = lcdc_read(&da8xx_fb_reg_base->raw_stat); in lcd_disable_raster()
267 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcd_disable_raster()
269 lcdc_write(stat, &da8xx_fb_reg_base->raw_stat); in lcd_disable_raster()
286 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); in lcd_blit()
289 reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl); in lcd_blit()
292 start = par->dma_start; in lcd_blit()
293 end = par->dma_end; in lcd_blit()
299 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | in lcd_blit()
303 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); in lcd_blit()
308 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcd_blit()
309 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcd_blit()
310 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); in lcd_blit()
311 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); in lcd_blit()
314 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcd_blit()
315 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcd_blit()
316 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); in lcd_blit()
317 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); in lcd_blit()
321 start = par->p_palette_base; in lcd_blit()
322 end = start + par->palette_sz - 1; in lcd_blit()
328 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | in lcd_blit()
330 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); in lcd_blit()
333 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcd_blit()
334 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcd_blit()
337 lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl); in lcd_blit()
338 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); in lcd_blit()
352 reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001; in lcd_cfg_dma()
370 return -EINVAL; in lcd_cfg_dma()
372 lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl); in lcd_cfg_dma()
381 /* Set the AC Bias Period and Number of Transitions per Interrupt */ in lcd_cfg_ac_bias()
382 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000; in lcd_cfg_ac_bias()
385 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_ac_bias()
393 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf; in lcd_cfg_horizontal_sync()
397 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); in lcd_cfg_horizontal_sync()
405 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff; in lcd_cfg_vertical_sync()
409 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); in lcd_cfg_vertical_sync()
417 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE | in lcd_cfg_display()
421 switch (cfg->p_disp_panel->panel_shade) { in lcd_cfg_display()
424 if (cfg->mono_8bit_mode) in lcd_cfg_display()
429 if (cfg->tft_alt_mode) in lcd_cfg_display()
434 if (cfg->stn_565_mode) in lcd_cfg_display()
439 return -EINVAL; in lcd_cfg_display()
446 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) | in lcd_cfg_display()
448 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set); in lcd_cfg_display()
451 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); in lcd_cfg_display()
453 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_display()
455 if (cfg->sync_ctrl) in lcd_cfg_display()
460 if (cfg->sync_edge) in lcd_cfg_display()
465 if (cfg->invert_line_clock) in lcd_cfg_display()
470 if (cfg->invert_frm_clock) in lcd_cfg_display()
475 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_display()
500 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0); in lcd_cfg_frame_buffer()
503 reg |= ((width >> 4) - 1) << 4; in lcd_cfg_frame_buffer()
505 width = (width >> 4) - 1; in lcd_cfg_frame_buffer()
508 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0); in lcd_cfg_frame_buffer()
512 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1); in lcd_cfg_frame_buffer()
513 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00); in lcd_cfg_frame_buffer()
514 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1); in lcd_cfg_frame_buffer()
518 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_frame_buffer()
519 reg |= ((height - 1) & 0x400) << 16; in lcd_cfg_frame_buffer()
520 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2); in lcd_cfg_frame_buffer()
524 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8); in lcd_cfg_frame_buffer()
534 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl); in lcd_cfg_frame_buffer()
543 par->palette_sz = 16 * 2; in lcd_cfg_frame_buffer()
547 par->palette_sz = 256 * 2; in lcd_cfg_frame_buffer()
551 return -EINVAL; in lcd_cfg_frame_buffer()
561 struct da8xx_fb_par *par = info->par; in fb_setcolreg()
562 unsigned short *palette = (unsigned short *) par->v_palette_base; in fb_setcolreg()
569 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) in fb_setcolreg()
572 if (info->var.bits_per_pixel == 8) { in fb_setcolreg()
585 } else if ((info->var.bits_per_pixel == 16) && regno < 16) { in fb_setcolreg()
586 red >>= (16 - info->var.red.length); in fb_setcolreg()
587 red <<= info->var.red.offset; in fb_setcolreg()
589 green >>= (16 - info->var.green.length); in fb_setcolreg()
590 green <<= info->var.green.offset; in fb_setcolreg()
592 blue >>= (16 - info->var.blue.length); in fb_setcolreg()
593 blue <<= info->var.blue.offset; in fb_setcolreg()
595 par->pseudo_palette[regno] = red | green | blue; in fb_setcolreg()
601 } else if (((info->var.bits_per_pixel == 32) && regno < 32) || in fb_setcolreg()
602 ((info->var.bits_per_pixel == 24) && regno < 24)) { in fb_setcolreg()
603 red >>= (24 - info->var.red.length); in fb_setcolreg()
604 red <<= info->var.red.offset; in fb_setcolreg()
606 green >>= (24 - info->var.green.length); in fb_setcolreg()
607 green <<= info->var.green.offset; in fb_setcolreg()
609 blue >>= (24 - info->var.blue.length); in fb_setcolreg()
610 blue <<= info->var.blue.offset; in fb_setcolreg()
612 par->pseudo_palette[regno] = red | green | blue; in fb_setcolreg()
633 lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl); in lcd_reset()
634 lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl); in lcd_reset()
637 lcdc_write(0, &da8xx_fb_reg_base->int_ena_set); in lcd_reset()
639 lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset); in lcd_reset()
640 lcdc_write(0, &da8xx_fb_reg_base->clk_reset); in lcd_reset()
651 div = lcd_clk / par->pxl_clk; in lcd_calc_clk_divider()
653 lcd_clk, div, par->pxl_clk); in lcd_calc_clk_divider()
657 (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl); in lcd_calc_clk_divider()
662 &da8xx_fb_reg_base->clk_ena); in lcd_calc_clk_divider()
676 if (panel->invert_pxl_clk) in lcd_init()
677 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) | in lcd_init()
679 &da8xx_fb_reg_base->raster_timing_2); in lcd_init()
681 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & in lcd_init()
683 &da8xx_fb_reg_base->raster_timing_2); in lcd_init()
686 ret = lcd_cfg_dma(cfg->dma_burst_sz); in lcd_init()
690 /* Configure the AC bias properties. */ in lcd_init()
691 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt); in lcd_init()
694 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp); in lcd_init()
695 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp); in lcd_init()
702 if ((QVGA != cfg->p_disp_panel->panel_type) && in lcd_init()
703 (WVGA != cfg->p_disp_panel->panel_type)) in lcd_init()
704 return -EINVAL; in lcd_init()
706 if (cfg->bpp <= cfg->p_disp_panel->max_bpp && in lcd_init()
707 cfg->bpp >= cfg->p_disp_panel->min_bpp) in lcd_init()
708 bpp = cfg->bpp; in lcd_init()
710 bpp = cfg->p_disp_panel->max_bpp; in lcd_init()
713 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width, in lcd_init()
714 (unsigned int)panel->height, bpp, in lcd_init()
715 cfg->raster_order); in lcd_init()
720 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) | in lcd_init()
721 (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl); in lcd_init()
728 struct da8xx_fb_par *par = da8xx_fb_info->par; in lcdc_dma_start()
729 lcdc_write(par->dma_start, in lcdc_dma_start()
730 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcdc_dma_start()
731 lcdc_write(par->dma_end, in lcdc_dma_start()
732 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcdc_dma_start()
734 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1); in lcdc_dma_start()
736 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1); in lcdc_dma_start()
741 struct da8xx_fb_par *par = da8xx_fb_info->par; in lcdc_irq_handler_rev01()
742 u32 stat = lcdc_read(&da8xx_fb_reg_base->stat); in lcdc_irq_handler_rev01()
748 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcdc_irq_handler_rev01()
761 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcdc_irq_handler_rev01()
764 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl); in lcdc_irq_handler_rev01()
766 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl); in lcdc_irq_handler_rev01()
772 lcdc_write(stat, &da8xx_fb_reg_base->stat); in lcdc_irq_handler_rev01()
777 lcdc_write(par->dma_start, in lcdc_irq_handler_rev01()
778 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcdc_irq_handler_rev01()
779 lcdc_write(par->dma_end, in lcdc_irq_handler_rev01()
780 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcdc_irq_handler_rev01()
781 par->vsync_flag = 1; in lcdc_irq_handler_rev01()
789 struct da8xx_fb_par *par = da8xx_fb_info->par; in lcdc_irq_handler_rev02()
790 u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat); in lcdc_irq_handler_rev02()
796 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); in lcdc_irq_handler_rev02()
798 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
810 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); in lcdc_irq_handler_rev02()
813 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) | in lcdc_irq_handler_rev02()
815 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr); in lcdc_irq_handler_rev02()
819 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
822 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat); in lcdc_irq_handler_rev02()
827 lcdc_write(par->dma_start, in lcdc_irq_handler_rev02()
828 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0); in lcdc_irq_handler_rev02()
829 lcdc_write(par->dma_end, in lcdc_irq_handler_rev02()
830 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0); in lcdc_irq_handler_rev02()
831 par->vsync_flag = 1; in lcdc_irq_handler_rev02()
832 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
835 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind); in lcdc_irq_handler_rev02()
855 --timeout; in wait_for_event()
860 return -1; in wait_for_event()
878 gpanel.winSizeX = lcd_panel->width; in video_hw_init()
879 gpanel.winSizeY = lcd_panel->height; in video_hw_init()
880 gpanel.plnSizeX = lcd_panel->width; in video_hw_init()
881 gpanel.plnSizeY = lcd_panel->height; in video_hw_init()
905 rev = lcdc_read(&da8xx_fb_reg_base->revid); in video_hw_init()
915 printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n", in video_hw_init()
924 da8xx_lcd_cfg->bpp); in video_hw_init()
936 da8xx_fb_info->par = p + sizeof(struct fb_info); in video_hw_init()
937 debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par); in video_hw_init()
939 par = da8xx_fb_info->par; in video_hw_init()
940 par->pxl_clk = lcd_panel->pxl_clk; in video_hw_init()
948 par->vram_size = lcd_panel->width * lcd_panel->height * in video_hw_init()
949 da8xx_lcd_cfg->bpp; in video_hw_init()
950 par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8; in video_hw_init()
952 par->vram_virt = malloc_cache_aligned(par->vram_size); in video_hw_init()
954 par->vram_phys = (dma_addr_t) par->vram_virt; in video_hw_init()
956 (unsigned int)par->vram_size, in video_hw_init()
957 (unsigned int)par->vram_virt); in video_hw_init()
958 if (!par->vram_virt) { in video_hw_init()
962 gd->fb_base = (int)par->vram_virt; in video_hw_init()
964 gpanel.frameAdrs = (unsigned int)par->vram_virt; in video_hw_init()
965 da8xx_fb_info->screen_base = (char *) par->vram_virt; in video_hw_init()
967 da8xx_fb_fix.smem_len = par->vram_size; in video_hw_init()
968 da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8; in video_hw_init()
970 par->dma_start = par->vram_phys; in video_hw_init()
971 par->dma_end = par->dma_start + lcd_panel->height * in video_hw_init()
972 da8xx_fb_fix.line_length - 1; in video_hw_init()
975 par->v_palette_base = malloc_cache_aligned(PALETTE_SIZE); in video_hw_init()
976 if (!par->v_palette_base) { in video_hw_init()
980 memset(par->v_palette_base, 0, PALETTE_SIZE); in video_hw_init()
981 par->p_palette_base = (unsigned int)par->v_palette_base; in video_hw_init()
984 da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp; in video_hw_init()
986 da8xx_fb_var.xres = lcd_panel->width; in video_hw_init()
987 da8xx_fb_var.xres_virtual = lcd_panel->width; in video_hw_init()
989 da8xx_fb_var.yres = lcd_panel->height; in video_hw_init()
990 da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS; in video_hw_init()
993 da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0; in video_hw_init()
994 da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp; in video_hw_init()
996 da8xx_fb_var.hsync_len = lcd_panel->hsw; in video_hw_init()
997 da8xx_fb_var.vsync_len = lcd_panel->vsw; in video_hw_init()
1000 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT; in video_hw_init()
1001 da8xx_fb_info->fix = da8xx_fb_fix; in video_hw_init()
1002 da8xx_fb_info->var = da8xx_fb_var; in video_hw_init()
1003 da8xx_fb_info->pseudo_palette = par->pseudo_palette; in video_hw_init()
1004 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ? in video_hw_init()
1008 memset((void *)par->vram_virt, 0, par->vram_size); in video_hw_init()
1011 lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat); in video_hw_init()
1013 lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat); in video_hw_init()
1014 debug("Palette at 0x%x size %d\n", par->p_palette_base, in video_hw_init()
1015 par->palette_sz); in video_hw_init()
1030 free(par->vram_virt); in video_hw_init()