1 // SPDX-License-Identifier: GPL-2.0+
12 #include "../anx98xx-edp.h"
14 #define DP_MAX_LINK_RATE		0x001
15 #define DP_MAX_LANE_COUNT		0x002
16 #define DP_MAX_LANE_COUNT_MASK		0x1f
22 static int anx6345_write(struct udevice *dev, unsigned int addr_off,  in anx6345_write()  argument
30 	msg.flags = 0;  in anx6345_write()
31 	buf[0] = reg_addr;  in anx6345_write()
35 	ret = dm_i2c_xfer(dev, &msg, 1);  in anx6345_write()
42 	return 0;  in anx6345_write()
45 static int anx6345_read(struct udevice *dev, unsigned int addr_off,  in anx6345_read()  argument
52 	msg[0].addr = addr_off;  in anx6345_read()
53 	msg[0].flags = 0;  in anx6345_read()
55 	msg[0].buf = &addr;  in anx6345_read()
56 	msg[0].len = 1;  in anx6345_read()
61 	ret = dm_i2c_xfer(dev, msg, 2);  in anx6345_read()
69 	return 0;  in anx6345_read()
72 static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr,  in anx6345_write_r0()  argument
75 	struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);  in anx6345_write_r0()
77 	return anx6345_write(dev, chip->chip_addr, reg_addr, value);  in anx6345_write_r0()
80 static int anx6345_read_r0(struct udevice *dev, unsigned char reg_addr,  in anx6345_read_r0()  argument
83 	struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);  in anx6345_read_r0()
85 	return anx6345_read(dev, chip->chip_addr, reg_addr, value);  in anx6345_read_r0()
88 static int anx6345_write_r1(struct udevice *dev, unsigned char reg_addr,  in anx6345_write_r1()  argument
91 	struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);  in anx6345_write_r1()
93 	return anx6345_write(dev, chip->chip_addr + 1, reg_addr, value);  in anx6345_write_r1()
96 static int anx6345_read_r1(struct udevice *dev, unsigned char reg_addr,  in anx6345_read_r1()  argument
99 	struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);  in anx6345_read_r1()
101 	return anx6345_read(dev, chip->chip_addr + 1, reg_addr, value);  in anx6345_read_r1()
104 static int anx6345_set_backlight(struct udevice *dev, int percent)  in anx6345_set_backlight()  argument
106 	return -ENOSYS;  in anx6345_set_backlight()
109 static int anx6345_aux_wait(struct udevice *dev)  in anx6345_aux_wait()  argument
111 	int ret = -ETIMEDOUT;  in anx6345_aux_wait()
116 		anx6345_read_r0(dev, ANX9804_DP_AUX_CH_CTL_2, &v);  in anx6345_aux_wait()
118 			ret = 0;  in anx6345_aux_wait()
122 	} while (retries--);  in anx6345_aux_wait()
129 	ret = -ETIMEDOUT;  in anx6345_aux_wait()
132 		anx6345_read_r1(dev, ANX9804_DP_INT_STA, &v);  in anx6345_aux_wait()
134 			ret = 0;  in anx6345_aux_wait()
138 	} while (retries--);  in anx6345_aux_wait()
146 	anx6345_write_r1(dev, ANX9804_DP_INT_STA, v);  in anx6345_aux_wait()
148 	anx6345_read_r0(dev, ANX9804_AUX_CH_STA, &v);  in anx6345_aux_wait()
149 	if ((v & ANX9804_AUX_STATUS_MASK) != 0) {  in anx6345_aux_wait()
151 		ret = -EIO;  in anx6345_aux_wait()
157 static void anx6345_aux_addr(struct udevice *dev, u32 addr)  in anx6345_aux_addr()  argument
161 	val = addr & 0xff;  in anx6345_aux_addr()
162 	anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_7_0, val);  in anx6345_aux_addr()
163 	val = (addr >> 8) & 0xff;  in anx6345_aux_addr()
164 	anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_15_8, val);  in anx6345_aux_addr()
165 	val = (addr >> 16) & 0x0f;  in anx6345_aux_addr()
166 	anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_19_16, val);  in anx6345_aux_addr()
169 static int anx6345_aux_transfer(struct udevice *dev, u8 req,  in anx6345_aux_transfer()  argument
177 		return -E2BIG;  in anx6345_aux_transfer()
185 		for (i = 0; i < len; i++)  in anx6345_aux_transfer()
186 			anx6345_write_r0(dev, ANX9804_BUF_DATA_0 + i, buf[i]);  in anx6345_aux_transfer()
189 	anx6345_aux_addr(dev, addr);  in anx6345_aux_transfer()
190 	anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_1, ctrl1);  in anx6345_aux_transfer()
191 	anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_2, ctrl2);  in anx6345_aux_transfer()
192 	ret = anx6345_aux_wait(dev);  in anx6345_aux_transfer()
199 		for (i = 0; i < len; i++)  in anx6345_aux_transfer()
200 			anx6345_read_r0(dev, ANX9804_BUF_DATA_0 + i, &buf[i]);  in anx6345_aux_transfer()
203 	return 0;  in anx6345_aux_transfer()
206 static int anx6345_read_aux_i2c(struct udevice *dev, u8 chip_addr,  in anx6345_read_aux_i2c()  argument
213 	for (i = 0; i < count; i += 16) {  in anx6345_read_aux_i2c()
214 		cur_cnt = (count - i) > 16 ? 16 : count - i;  in anx6345_read_aux_i2c()
216 		ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_MOT,  in anx6345_read_aux_i2c()
223 		ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_READ,  in anx6345_read_aux_i2c()
232 	return 0;  in anx6345_read_aux_i2c()
235 static int anx6345_read_dpcd(struct udevice *dev, u32 reg, u8 *val)  in anx6345_read_dpcd()  argument
239 	ret = anx6345_aux_transfer(dev,  in anx6345_read_dpcd()
248 	return 0;  in anx6345_read_dpcd()
251 static int anx6345_read_edid(struct udevice *dev, u8 *buf, int size)  in anx6345_read_edid()  argument
253 	struct anx6345_priv *priv = dev_get_priv(dev);  in anx6345_read_edid()
257 	memcpy(buf, priv->edid, size);  in anx6345_read_edid()
262 static int anx6345_attach(struct udevice *dev)  in anx6345_attach()  argument
264 	/* No-op */  in anx6345_attach()
265 	return 0;  in anx6345_attach()
268 static int anx6345_enable(struct udevice *dev)  in anx6345_enable()  argument
273 	struct anx6345_priv *priv = dev_get_priv(dev);  in anx6345_enable()
276 	ret = video_bridge_set_active(dev, true);  in anx6345_enable()
281 	anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 1);  in anx6345_enable()
283 	anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 0);  in anx6345_enable()
285 	/* Write 0 to the powerdown reg (powerup everything) */  in anx6345_enable()
286 	anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, 0);  in anx6345_enable()
288 	ret = anx6345_read_r1(dev, ANX9804_DEV_IDH_REG, &chipid);  in anx6345_enable()
293 	case 0x63:  in anx6345_enable()
298 		return -ENODEV;  in anx6345_enable()
301 	for (i = 0; i < 100; i++) {  in anx6345_enable()
302 		anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);  in anx6345_enable()
303 		anx6345_write_r0(dev, ANX9804_SYS_CTRL2_REG, c);  in anx6345_enable()
304 		anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);  in anx6345_enable()
305 		if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)  in anx6345_enable()
314 	anx6345_write_r0(dev, ANX9804_PLL_CTRL_REG, 0x00);  in anx6345_enable()
315 	anx6345_write_r1(dev, ANX9804_ANALOG_DEBUG_REG1, 0x70);  in anx6345_enable()
316 	anx6345_write_r0(dev, ANX9804_LINK_DEBUG_REG, 0x30);  in anx6345_enable()
319 	anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,  in anx6345_enable()
323 	anx6345_write_r0(dev, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);  in anx6345_enable()
324 	anx6345_write_r0(dev, ANX9804_TRAINING_LANE0_SET_REG, 0x00);  in anx6345_enable()
325 	anx6345_write_r0(dev, ANX9804_TRAINING_LANE1_SET_REG, 0x00);  in anx6345_enable()
326 	anx6345_write_r0(dev, ANX9804_TRAINING_LANE2_SET_REG, 0x00);  in anx6345_enable()
327 	anx6345_write_r0(dev, ANX9804_TRAINING_LANE3_SET_REG, 0x00);  in anx6345_enable()
330 	anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG,  in anx6345_enable()
332 	anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG, 0);  in anx6345_enable()
335 	anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);  in anx6345_enable()
336 	anx6345_write_r0(dev, ANX9804_HDCP_CONTROL_0_REG, 0x00);  in anx6345_enable()
337 	anx6345_write_r0(dev, 0xa7, 0x00);  in anx6345_enable()
339 	anx6345_read_aux_i2c(dev, 0x50, 0x0, EDID_SIZE, priv->edid);  in anx6345_enable()
340 	if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) {  in anx6345_enable()
342 		return -EIO;  in anx6345_enable()
347 		colordepth = 0x00; /* 6 bit */  in anx6345_enable()
349 		colordepth = 0x10; /* 8 bit */  in anx6345_enable()
350 	anx6345_write_r1(dev, ANX9804_VID_CTRL2_REG, colordepth);  in anx6345_enable()
352 	if (anx6345_read_dpcd(dev, DP_MAX_LINK_RATE, &data_rate)) {  in anx6345_enable()
354 		return -EIO;  in anx6345_enable()
357 	if (anx6345_read_dpcd(dev, DP_MAX_LANE_COUNT, &lanes)) {  in anx6345_enable()
359 		return -EIO;  in anx6345_enable()
364 	/* Set data-rate / lanes */  in anx6345_enable()
365 	anx6345_write_r0(dev, ANX9804_LINK_BW_SET_REG, data_rate);  in anx6345_enable()
366 	anx6345_write_r0(dev, ANX9804_LANE_COUNT_SET_REG, lanes);  in anx6345_enable()
369 	anx6345_write_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG,  in anx6345_enable()
372 	for (i = 0; i < 100; i++) {  in anx6345_enable()
373 		anx6345_read_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG, &c);  in anx6345_enable()
374 		if ((chipid == 0x63) && (c & 0x80) == 0)  in anx6345_enable()
381 		return -ENODEV;  in anx6345_enable()
385 	anx6345_write_r1(dev, ANX9804_VID_CTRL1_REG,  in anx6345_enable()
388 	anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,  in anx6345_enable()
394 	return 0;  in anx6345_enable()
397 static int anx6345_probe(struct udevice *dev)  in anx6345_probe()  argument
399 	if (device_get_uclass_id(dev->parent) != UCLASS_I2C)  in anx6345_probe()
400 		return -EPROTONOSUPPORT;  in anx6345_probe()
402 	return anx6345_enable(dev);  in anx6345_probe()