1 // SPDX-License-Identifier: GPL-2.0+
32 	struct display_timing timing;  member
108 		struct bmp_color_table_entry cte = bmp->color_table[i];  in lcd_set_cmap()
114 static void atmel_fb_init(ulong addr, struct display_timing *timing, int bpix,  in atmel_fb_init()  argument
134 	value = (timing->hactive.typ * timing->vactive.typ *  in atmel_fb_init()
136 	value |= ((ATMEL_LCDC_DMA_BURST_LEN - 1) << ATMEL_LCDC_BLENGTH_OFFSET);  in atmel_fb_init()
140 	value = get_lcdc_clk_rate(0) / timing->pixelclock.typ;  in atmel_fb_init()
141 	if (get_lcdc_clk_rate(0) % timing->pixelclock.typ)  in atmel_fb_init()
143 	value = (value / 2) - 1;  in atmel_fb_init()
156 	if (!(timing->flags & DISPLAY_FLAGS_HSYNC_HIGH))  in atmel_fb_init()
158 	if (!(timing->flags & DISPLAY_FLAGS_VSYNC_HIGH))  in atmel_fb_init()
163 	/* Vertical timing */  in atmel_fb_init()
164 	value = (timing->vsync_len.typ - 1) << ATMEL_LCDC_VPW_OFFSET;  in atmel_fb_init()
165 	value |= timing->vback_porch.typ << ATMEL_LCDC_VBP_OFFSET;  in atmel_fb_init()
166 	value |= timing->vfront_porch.typ;  in atmel_fb_init()
171 	/* Horizontal timing */  in atmel_fb_init()
172 	value = (timing->hfront_porch.typ - 1) << ATMEL_LCDC_HFP_OFFSET;  in atmel_fb_init()
173 	value |= (timing->hsync_len.typ - 1) << ATMEL_LCDC_HPW_OFFSET;  in atmel_fb_init()
174 	value |= (timing->hback_porch.typ - 1);  in atmel_fb_init()
178 	value = (timing->hactive.typ - 1) << ATMEL_LCDC_HOZVAL_OFFSET;  in atmel_fb_init()
179 	value |= timing->vactive.typ - 1;  in atmel_fb_init()
183 	value = ATMEL_LCDC_FIFO_SIZE - (2 * ATMEL_LCDC_DMA_BURST_LEN + 3);  in atmel_fb_init()
211 	struct display_timing timing;  in lcd_ctrl_init()  local
213 	timing.flags = 0;  in lcd_ctrl_init()
215 		timing.flags |= DISPLAY_FLAGS_HSYNC_HIGH;  in lcd_ctrl_init()
217 		timing.flags |= DISPLAY_FLAGS_VSYNC_LOW;  in lcd_ctrl_init()
218 	timing.pixelclock.typ = panel_info.vl_clk;  in lcd_ctrl_init()
220 	timing.hactive.typ = panel_info.vl_col;  in lcd_ctrl_init()
221 	timing.hfront_porch.typ = panel_info.vl_right_margin;  in lcd_ctrl_init()
222 	timing.hback_porch.typ = panel_info.vl_left_margin;  in lcd_ctrl_init()
223 	timing.hsync_len.typ = panel_info.vl_hsync_len;  in lcd_ctrl_init()
225 	timing.vactive.typ = panel_info.vl_row;  in lcd_ctrl_init()
226 	timing.vfront_porch.typ = panel_info.vl_clk;  in lcd_ctrl_init()
227 	timing.vback_porch.typ = panel_info.vl_clk;  in lcd_ctrl_init()
228 	timing.vsync_len.typ = panel_info.vl_clk;  in lcd_ctrl_init()
230 	atmel_fb_init(panel_info.mmio, &timing, panel_info.vl_bpix,  in lcd_ctrl_init()
248 	struct display_timing *timing = &priv->timing;  in atmel_fb_lcd_probe()  local
251 	 * For now some values are hard-coded. We could use the device tree  in atmel_fb_lcd_probe()
252 	 * bindings in simple-framebuffer.txt to specify the format/bpp and  in atmel_fb_lcd_probe()
253 	 * some Atmel-specific binding for tft and cont_pol_low.  in atmel_fb_lcd_probe()
255 	atmel_fb_init(ATMEL_BASE_LCDC, timing, VIDEO_BPP16, true, false,  in atmel_fb_lcd_probe()
256 		      uc_plat->base);  in atmel_fb_lcd_probe()
257 	uc_priv->xsize = timing->hactive.typ;  in atmel_fb_lcd_probe()
258 	uc_priv->ysize = timing->vactive.typ;  in atmel_fb_lcd_probe()
259 	uc_priv->bpix = VIDEO_BPP16;  in atmel_fb_lcd_probe()
261 	debug("LCD frame buffer at %lx, size %x, %dx%d pixels\n", uc_plat->base,  in atmel_fb_lcd_probe()
262 	      uc_plat->size, uc_priv->xsize, uc_priv->ysize);  in atmel_fb_lcd_probe()
271 	struct display_timing *timing = &priv->timing;  in atmel_fb_ofdata_to_platdata()  local
272 	const void *blob = gd->fdt_blob;  in atmel_fb_ofdata_to_platdata()
275 					 plat->timing_index, timing)) {  in atmel_fb_ofdata_to_platdata()
276 		debug("%s: Failed to decode display timing\n", __func__);  in atmel_fb_ofdata_to_platdata()
277 		return -EINVAL;  in atmel_fb_ofdata_to_platdata()
287 	uc_plat->size = LCD_MAX_WIDTH * LCD_MAX_HEIGHT *  in atmel_fb_lcd_bind()
289 	debug("%s: Frame buffer size %x\n", __func__, uc_plat->size);  in atmel_fb_lcd_bind()
295 	{ .compatible = "atmel,at91sam9g45-lcdc" },