Lines Matching +full:16 +full:bpp
46 #define SURF_UPPER_BOUND(x,y,bpp) (((((x) * (((y) + 15) & ~15) * (bpp)/8) + RADEON_BUFFER_ALIGN) \ argument
48 #define RADEON_CRT_PITCH(width, bpp) ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) | \ argument
49 ((((width) * (bpp) + ((bpp) * 8 - 1)) / ((bpp) * 8)) << 16))
52 (((((htotal) / 8) - 1) & 0x3ff) | (((((hdisp) / 8) - 1) & 0x1ff) << 16))
54 (((hsync_srtr) & 0x1fff) | (((hsync_wid) & 0x3f) << 16))
56 ((((vtotal) - 1) & 0xffff) | (((vdisp) - 1) << 16))
58 ((((vsync_srtr) - 1) & 0xfff) | (((vsync_wid) & 0x1f) << 16))
114 tmp = ((((tom >> 16) - (tom & 0xffff) + 1) << 6) * 1024); in radeon_identify_vram()
118 OUTREG(DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); in radeon_identify_vram()
119 OUTREG(CRTC2_DISPLAY_BASE_ADDR, (tom & 0xffff) << 16); in radeon_identify_vram()
120 OUTREG(OV0_BASE_ADDR, (tom & 0xffff) << 16); in radeon_identify_vram()
359 void radeon_setmode_9200(int vesa_idx, int bpp) in radeon_setmode_9200() argument
368 switch (bpp) { in radeon_setmode_9200()
376 case 16: in radeon_setmode_9200()
402 * for this mode pitch expands to the same value for 32, 16 and 8 bpp, in radeon_setmode_9200()
406 switch (bpp) { in radeon_setmode_9200()
408 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16); in radeon_setmode_9200()
411 case 16: in radeon_setmode_9200()
412 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16); in radeon_setmode_9200()
413 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16); in radeon_setmode_9200()
415 default: /* 8 bpp */ in radeon_setmode_9200()
416 mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16); in radeon_setmode_9200()
435 /* also same pitch value for 32, 16 and 8 bpp */ in radeon_setmode_9200()
437 switch (bpp) { in radeon_setmode_9200()
439 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16); in radeon_setmode_9200()
442 case 16: in radeon_setmode_9200()
443 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16); in radeon_setmode_9200()
444 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16); in radeon_setmode_9200()
446 default: /* 8 bpp */ in radeon_setmode_9200()
447 mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); in radeon_setmode_9200()
460 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16); in radeon_setmode_9200()
465 switch (bpp) { in radeon_setmode_9200()
468 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16); in radeon_setmode_9200()
471 case 16: in radeon_setmode_9200()
472 mode->crtc_pitch = RADEON_CRT_PITCH(896,16); in radeon_setmode_9200()
473 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16); in radeon_setmode_9200()
474 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16); in radeon_setmode_9200()
476 default: /* 8 bpp */ in radeon_setmode_9200()
478 mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); in radeon_setmode_9200()
497 /* also same pitch value for 32, 16 and 8 bpp */ in radeon_setmode_9200()
499 switch (bpp) { in radeon_setmode_9200()
501 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16); in radeon_setmode_9200()
504 case 16: in radeon_setmode_9200()
505 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16); in radeon_setmode_9200()
506 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16); in radeon_setmode_9200()
508 default: /* 8 bpp */ in radeon_setmode_9200()
540 if (bpp > 8) in radeon_setmode_9200()
558 PCI_VENDOR_ID_ATI, did, (pdev >> 16) & 0xff, in radeon_probe()
576 rinfo->fb_local_base = INREG(MC_FB_LOCATION) << 16; in radeon_probe()
643 videomode = (int) simple_strtoul (penv, NULL, 16); in video_hw_init()
699 case 16: in video_hw_init()
758 OUTREG(PALETTE_DATA, (r << 16) | (g << 8) | b); in video_set_lut()