Lines Matching refs:hw_ep
196 struct musb_hw_ep *hw_ep = qh->hw_ep; in musb_start_urb() local
199 int epnum = hw_ep->epnum; in musb_start_urb()
242 musb_ep_set_qh(hw_ep, is_in, qh); in musb_start_urb()
283 hw_ep->tx_channel ? "dma" : "pio"); in musb_start_urb()
285 if (!hw_ep->tx_channel) in musb_start_urb()
286 musb_h_tx_start(hw_ep); in musb_start_urb()
288 musb_h_tx_dma_start(hw_ep); in musb_start_urb()
316 void __iomem *epio = qh->hw_ep->regs; in musb_save_toggle()
340 struct musb_hw_ep *hw_ep, int is_in) in musb_advance_schedule() argument
342 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in); in musb_advance_schedule()
343 struct musb_hw_ep *ep = qh->hw_ep; in musb_advance_schedule()
421 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); in musb_advance_schedule()
426 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) in musb_h_flush_rxfifo() argument
438 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_h_flush_rxfifo()
439 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_h_flush_rxfifo()
442 return musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_h_flush_rxfifo()
457 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_host_packet_rx() local
458 void __iomem *epio = hw_ep->regs; in musb_host_packet_rx()
459 struct musb_qh *qh = hw_ep->in_qh; in musb_host_packet_rx()
528 musb_read_fifo(hw_ep, length, buf); in musb_host_packet_rx()
533 musb_h_flush_rxfifo(hw_ep, csr); in musb_host_packet_rx()
617 struct musb_hw_ep *hw_ep, struct musb_qh *qh, in musb_tx_dma_program() argument
620 struct dma_channel *channel = hw_ep->tx_channel; in musb_tx_dma_program()
621 void __iomem *epio = hw_ep->regs; in musb_tx_dma_program()
668 hw_ep->tx_channel = NULL; in musb_tx_dma_program()
690 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_ep_program() local
691 void __iomem *epio = hw_ep->regs; in musb_ep_program()
692 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out); in musb_ep_program()
708 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; in musb_ep_program()
711 dma_controller, hw_ep, is_out); in musb_ep_program()
713 hw_ep->tx_channel = dma_channel; in musb_ep_program()
715 hw_ep->rx_channel = dma_channel; in musb_ep_program()
737 musb_h_tx_flush_fifo(hw_ep); in musb_ep_program()
767 musb_h_ep0_flush_fifo(hw_ep); in musb_ep_program()
784 hw_ep->max_packet_sz_tx); in musb_ep_program()
787 | ((hw_ep->max_packet_sz_tx / in musb_ep_program()
802 load_count = min((u32) hw_ep->max_packet_sz_tx, in musb_ep_program()
808 hw_ep, qh, urb, offset, len)) in musb_ep_program()
814 musb_write_fifo(hw_ep, load_count, buf); in musb_ep_program()
824 if (hw_ep->rx_reinit) { in musb_ep_program()
825 musb_rx_reinit(musb, qh, hw_ep); in musb_ep_program()
837 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
843 hw_ep->epnum, csr); in musb_ep_program()
857 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_ep_program()
858 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
871 hw_ep->rx_channel = dma_channel = NULL; in musb_ep_program()
878 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_ep_program()
879 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
893 struct musb_hw_ep *hw_ep = musb->control_ep; in musb_h_ep0_continue() local
894 struct musb_qh *qh = hw_ep->in_qh; in musb_h_ep0_continue()
905 musb_read_fifo(hw_ep, fifo_count, fifo_dest); in musb_h_ep0_continue()
944 musb_write_fifo(hw_ep, fifo_count, fifo_dest); in musb_h_ep0_continue()
970 struct musb_hw_ep *hw_ep = musb->control_ep; in musb_h_ep0_irq() local
971 void __iomem *epio = hw_ep->regs; in musb_h_ep0_irq()
972 struct musb_qh *qh = hw_ep->in_qh; in musb_h_ep0_irq()
1032 musb_h_ep0_flush_fifo(hw_ep); in musb_h_ep0_irq()
1046 musb_h_ep0_flush_fifo(hw_ep); in musb_h_ep0_irq()
1079 musb_advance_schedule(musb, urb, hw_ep, 1); in musb_h_ep0_irq()
1109 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_host_tx() local
1110 void __iomem *epio = hw_ep->regs; in musb_host_tx()
1111 struct musb_qh *qh = hw_ep->out_qh; in musb_host_tx()
1128 dma = is_dma_capable() ? hw_ep->tx_channel : NULL; in musb_host_tx()
1173 musb_h_tx_flush_fifo(hw_ep); in musb_host_tx()
1310 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT); in musb_host_tx()
1313 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, in musb_host_tx()
1316 musb_h_tx_dma_start(hw_ep); in musb_host_tx()
1335 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); in musb_host_tx()
1434 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_host_rx() local
1435 void __iomem *epio = hw_ep->regs; in musb_host_rx()
1436 struct musb_qh *qh = hw_ep->in_qh; in musb_host_rx()
1449 dma = is_dma_capable() ? hw_ep->rx_channel : NULL; in musb_host_rx()
1463 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); in musb_host_rx()
1503 musb_bulk_rx_nak_timeout(musb, hw_ep); in musb_host_rx()
1531 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG); in musb_host_rx()
1580 musb_writew(hw_ep->regs, MUSB_RXCSR, val); in musb_host_rx()
1696 if (rx_count < hw_ep->max_packet_sz_rx) { in musb_host_rx()
1747 hw_ep->rx_channel = NULL; in musb_host_rx()
1773 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN); in musb_host_rx()
1790 struct musb_hw_ep *hw_ep = NULL; in musb_schedule() local
1799 hw_ep = musb->control_ep; in musb_schedule()
1815 for (epnum = 1, hw_ep = musb->endpoints + 1; in musb_schedule()
1817 epnum++, hw_ep++) { in musb_schedule()
1820 if (musb_ep_get_qh(hw_ep, is_in) != NULL) in musb_schedule()
1823 if (hw_ep == musb->bulk_ep) in musb_schedule()
1827 diff = hw_ep->max_packet_sz_rx; in musb_schedule()
1829 diff = hw_ep->max_packet_sz_tx; in musb_schedule()
1846 hw_ep = musb->endpoints + epnum; in musb_schedule()
1848 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE) in musb_schedule()
1860 hw_ep = musb->bulk_ep; in musb_schedule()
1883 hw_ep = musb->endpoints + best_end; in musb_schedule()
1891 qh->hw_ep = hw_ep; in musb_schedule()
2123 struct musb_hw_ep *ep = qh->hw_ep;
2222 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2265 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2281 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);