Lines Matching +full:role +full:- +full:switch +full:- +full:default +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2005-2006 by Texas Instruments
7 * Copyright (C) 2006-2007 Nokia Corporation
8 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
20 #include <linux/dma-mapping.h>
24 #include "linux-compat.h"
25 #include "usb-compat.h"
32 /* MUSB HOST status 22-mar-2006
34 * - There's still lots of partial code duplication for fault paths, so
37 * - PIO mostly behaved when last tested.
44 * - DMA (CPPI) ... partially behaves, not currently recommended
49 * - DMA (Mentor/OMAP) ...has at least toggle update problems
51 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
54 * - Not tested with HNP, but some SRP paths seem to behave.
56 * NOTE 24-August-2006:
58 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
61 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
62 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
91 struct musb *musb = ep->musb; in musb_h_tx_flush_fifo()
92 void __iomem *epio = ep->regs; in musb_h_tx_flush_fifo()
100 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr); in musb_h_tx_flush_fifo()
105 if (WARN(retries-- < 1, in musb_h_tx_flush_fifo()
107 ep->epnum, csr)) in musb_h_tx_flush_fifo()
115 void __iomem *epio = ep->regs; in musb_h_ep0_flush_fifo()
127 } while (--retries); in musb_h_ep0_flush_fifo()
130 ep->epnum, csr); in musb_h_ep0_flush_fifo()
145 if (ep->epnum) { in musb_h_tx_start()
146 txcsr = musb_readw(ep->regs, MUSB_TXCSR); in musb_h_tx_start()
148 musb_writew(ep->regs, MUSB_TXCSR, txcsr); in musb_h_tx_start()
151 musb_writew(ep->regs, MUSB_CSR0, txcsr); in musb_h_tx_start()
161 txcsr = musb_readw(ep->regs, MUSB_TXCSR); in musb_h_tx_dma_start()
165 musb_writew(ep->regs, MUSB_TXCSR, txcsr); in musb_h_tx_dma_start()
170 if (is_in != 0 || ep->is_shared_fifo) in musb_ep_set_qh()
171 ep->in_qh = qh; in musb_ep_set_qh()
172 if (is_in == 0 || ep->is_shared_fifo) in musb_ep_set_qh()
173 ep->out_qh = qh; in musb_ep_set_qh()
178 return is_in ? ep->in_qh : ep->out_qh; in musb_ep_get_qh()
192 void __iomem *mbase = musb->mregs; in musb_start_urb()
194 void *buf = urb->transfer_buffer; in musb_start_urb()
196 struct musb_hw_ep *hw_ep = qh->hw_ep; in musb_start_urb()
197 unsigned pipe = urb->pipe; in musb_start_urb()
199 int epnum = hw_ep->epnum; in musb_start_urb()
202 qh->offset = 0; in musb_start_urb()
203 qh->segsize = 0; in musb_start_urb()
206 switch (qh->type) { in musb_start_urb()
210 musb->ep0_stage = MUSB_EP0_START; in musb_start_urb()
211 buf = urb->setup_packet; in musb_start_urb()
216 qh->iso_idx = 0; in musb_start_urb()
217 qh->frame = 0; in musb_start_urb()
218 offset = urb->iso_frame_desc[0].offset; in musb_start_urb()
219 len = urb->iso_frame_desc[0].length; in musb_start_urb()
222 default: /* bulk, interrupt */ in musb_start_urb()
224 buf = urb->transfer_buffer + urb->actual_length; in musb_start_urb()
225 len = urb->transfer_buffer_length - urb->actual_length; in musb_start_urb()
228 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n", in musb_start_urb()
229 qh, urb, address, qh->epnum, in musb_start_urb()
231 ({char *s; switch (qh->type) { in musb_start_urb()
233 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break; in musb_start_urb()
235 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break; in musb_start_urb()
237 default: s = "-intr"; break; in musb_start_urb()
250 switch (qh->type) { in musb_start_urb()
255 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n"); in musb_start_urb()
261 if ((urb->transfer_flags & URB_ISO_ASAP) in musb_start_urb()
262 || (frame >= urb->start_frame)) { in musb_start_urb()
264 * this code; and we don't init urb->start_frame... in musb_start_urb()
266 qh->frame = 0; in musb_start_urb()
270 qh->frame = urb->start_frame; in musb_start_urb()
272 dev_dbg(musb->controller, "SOF for %d\n", epnum); in musb_start_urb()
280 default: in musb_start_urb()
282 dev_dbg(musb->controller, "Start TX%d %s\n", epnum, in musb_start_urb()
283 hw_ep->tx_channel ? "dma" : "pio"); in musb_start_urb()
285 if (!hw_ep->tx_channel) in musb_start_urb()
294 __releases(musb->lock) in musb_giveback()
295 __acquires(musb->lock) in musb_giveback()
297 dev_dbg(musb->controller, in musb_giveback()
299 urb, urb->complete, status, in musb_giveback()
300 usb_pipedevice(urb->pipe), in musb_giveback()
301 usb_pipeendpoint(urb->pipe), in musb_giveback()
302 usb_pipein(urb->pipe) ? "in" : "out", in musb_giveback()
303 urb->actual_length, urb->transfer_buffer_length in musb_giveback()
307 spin_unlock(&musb->lock); in musb_giveback()
309 spin_lock(&musb->lock); in musb_giveback()
316 void __iomem *epio = qh->hw_ep->regs; in musb_save_toggle()
329 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0); in musb_save_toggle()
343 struct musb_hw_ep *ep = qh->hw_ep; in musb_advance_schedule()
344 int ready = qh->is_ready; in musb_advance_schedule()
347 status = (urb->status == -EINPROGRESS) ? 0 : urb->status; in musb_advance_schedule()
350 switch (qh->type) { in musb_advance_schedule()
357 if (status == 0 && urb->error_count) in musb_advance_schedule()
358 status = -EXDEV; in musb_advance_schedule()
363 qh->is_ready = 0; in musb_advance_schedule()
365 qh->is_ready = ready; in musb_advance_schedule()
368 * invalidate qh as soon as list_empty(&hep->urb_list) in musb_advance_schedule()
370 if (list_empty(&qh->hep->urb_list)) { in musb_advance_schedule()
372 struct dma_controller *dma = musb->dma_controller; in musb_advance_schedule()
375 ep->rx_reinit = 1; in musb_advance_schedule()
376 if (ep->rx_channel) { in musb_advance_schedule()
377 dma->channel_release(ep->rx_channel); in musb_advance_schedule()
378 ep->rx_channel = NULL; in musb_advance_schedule()
381 ep->tx_reinit = 1; in musb_advance_schedule()
382 if (ep->tx_channel) { in musb_advance_schedule()
383 dma->channel_release(ep->tx_channel); in musb_advance_schedule()
384 ep->tx_channel = NULL; in musb_advance_schedule()
390 qh->hep->hcpriv = NULL; in musb_advance_schedule()
392 switch (qh->type) { in musb_advance_schedule()
399 if (qh->mux == 1) { in musb_advance_schedule()
400 head = qh->ring.prev; in musb_advance_schedule()
401 list_del(&qh->ring); in musb_advance_schedule()
410 * de-allocated if it's tracked and allocated; in musb_advance_schedule()
419 if (qh != NULL && qh->is_ready) { in musb_advance_schedule()
420 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n", in musb_advance_schedule()
421 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh)); in musb_advance_schedule()
438 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_h_flush_rxfifo()
439 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_h_flush_rxfifo()
442 return musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_h_flush_rxfifo()
457 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_host_packet_rx()
458 void __iomem *epio = hw_ep->regs; in musb_host_packet_rx()
459 struct musb_qh *qh = hw_ep->in_qh; in musb_host_packet_rx()
460 int pipe = urb->pipe; in musb_host_packet_rx()
461 void *buffer = urb->transfer_buffer; in musb_host_packet_rx()
465 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count, in musb_host_packet_rx()
466 urb->transfer_buffer, qh->offset, in musb_host_packet_rx()
467 urb->transfer_buffer_length); in musb_host_packet_rx()
476 status = -EILSEQ; in musb_host_packet_rx()
477 urb->error_count++; in musb_host_packet_rx()
480 d = urb->iso_frame_desc + qh->iso_idx; in musb_host_packet_rx()
481 buf = buffer + d->offset; in musb_host_packet_rx()
482 length = d->length; in musb_host_packet_rx()
485 status = -EOVERFLOW; in musb_host_packet_rx()
486 urb->error_count++; in musb_host_packet_rx()
488 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); in musb_host_packet_rx()
492 urb->actual_length += length; in musb_host_packet_rx()
493 d->actual_length = length; in musb_host_packet_rx()
495 d->status = status; in musb_host_packet_rx()
498 done = (++qh->iso_idx >= urb->number_of_packets); in musb_host_packet_rx()
501 /* non-isoch */ in musb_host_packet_rx()
502 buf = buffer + qh->offset; in musb_host_packet_rx()
503 length = urb->transfer_buffer_length - qh->offset; in musb_host_packet_rx()
505 if (urb->status == -EINPROGRESS) in musb_host_packet_rx()
506 urb->status = -EOVERFLOW; in musb_host_packet_rx()
507 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length); in musb_host_packet_rx()
511 urb->actual_length += length; in musb_host_packet_rx()
512 qh->offset += length; in musb_host_packet_rx()
515 done = (urb->actual_length == urb->transfer_buffer_length) in musb_host_packet_rx()
516 || (rx_count < qh->maxpacket) in musb_host_packet_rx()
517 || (urb->status != -EINPROGRESS); in musb_host_packet_rx()
519 && (urb->status == -EINPROGRESS) in musb_host_packet_rx()
520 && (urb->transfer_flags & URB_SHORT_NOT_OK) in musb_host_packet_rx()
521 && (urb->actual_length in musb_host_packet_rx()
522 < urb->transfer_buffer_length)) in musb_host_packet_rx()
523 urb->status = -EREMOTEIO; in musb_host_packet_rx()
551 * the busy/not-empty tests are basically paranoia.
563 /* if programmed for Tx, put it in RX mode */ in musb_rx_reinit()
564 if (ep->is_shared_fifo) { in musb_rx_reinit()
565 csr = musb_readw(ep->regs, MUSB_TXCSR); in musb_rx_reinit()
568 csr = musb_readw(ep->regs, MUSB_TXCSR); in musb_rx_reinit()
569 musb_writew(ep->regs, MUSB_TXCSR, in musb_rx_reinit()
574 * Clear the MODE bit (and everything else) to enable Rx. in musb_rx_reinit()
578 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE); in musb_rx_reinit()
579 musb_writew(ep->regs, MUSB_TXCSR, 0); in musb_rx_reinit()
583 csr = musb_readw(ep->regs, MUSB_RXCSR); in musb_rx_reinit()
585 WARNING("rx%d, packet/%d ready?\n", ep->epnum, in musb_rx_reinit()
586 musb_readw(ep->regs, MUSB_RXCOUNT)); in musb_rx_reinit()
592 if (musb->is_multipoint) { in musb_rx_reinit()
593 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg); in musb_rx_reinit()
594 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg); in musb_rx_reinit()
595 musb_write_rxhubport(ep->target_regs, qh->h_port_reg); in musb_rx_reinit()
598 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg); in musb_rx_reinit()
601 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg); in musb_rx_reinit()
602 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg); in musb_rx_reinit()
605 * to disable double buffer mode. in musb_rx_reinit()
607 if (musb->double_buffer_not_ok) in musb_rx_reinit()
608 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx); in musb_rx_reinit()
610 musb_writew(ep->regs, MUSB_RXMAXP, in musb_rx_reinit()
611 qh->maxpacket | ((qh->hb_mult - 1) << 11)); in musb_rx_reinit()
613 ep->rx_reinit = 0; in musb_rx_reinit()
620 struct dma_channel *channel = hw_ep->tx_channel; in musb_tx_dma_program()
621 void __iomem *epio = hw_ep->regs; in musb_tx_dma_program()
622 u16 pkt_size = qh->maxpacket; in musb_tx_dma_program()
624 u8 mode; in musb_tx_dma_program() local
627 if (length > channel->max_len) in musb_tx_dma_program()
628 length = channel->max_len; in musb_tx_dma_program()
632 mode = 1; in musb_tx_dma_program()
635 if (qh->hb_mult == 1) in musb_tx_dma_program()
638 mode = 0; in musb_tx_dma_program()
642 channel->desired_mode = mode; in musb_tx_dma_program()
648 channel->actual_len = 0; in musb_tx_dma_program()
651 * TX uses "RNDIS" mode automatically but needs help in musb_tx_dma_program()
652 * to identify the zero-length-final-packet case. in musb_tx_dma_program()
654 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0; in musb_tx_dma_program()
657 qh->segsize = length; in musb_tx_dma_program()
665 if (!dma->channel_program(channel, pkt_size, mode, in musb_tx_dma_program()
666 urb->transfer_dma + offset, length)) { in musb_tx_dma_program()
667 dma->channel_release(channel); in musb_tx_dma_program()
668 hw_ep->tx_channel = NULL; in musb_tx_dma_program()
689 void __iomem *mbase = musb->mregs; in musb_ep_program()
690 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_ep_program()
691 void __iomem *epio = hw_ep->regs; in musb_ep_program()
693 u16 packet_sz = qh->maxpacket; in musb_ep_program()
695 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s " in musb_ep_program()
697 is_out ? "-->" : "<--", in musb_ep_program()
698 epnum, urb, urb->dev->speed, in musb_ep_program()
699 qh->addr_reg, qh->epnum, is_out ? "out" : "in", in musb_ep_program()
700 qh->h_addr_reg, qh->h_port_reg, in musb_ep_program()
706 dma_controller = musb->dma_controller; in musb_ep_program()
708 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel; in musb_ep_program()
710 dma_channel = dma_controller->channel_alloc( in musb_ep_program()
713 hw_ep->tx_channel = dma_channel; in musb_ep_program()
715 hw_ep->rx_channel = dma_channel; in musb_ep_program()
736 /* flush all old state, set default */ in musb_ep_program()
754 if (usb_gettoggle(urb->dev, qh->epnum, 1)) in musb_ep_program()
771 if (musb->is_multipoint) { in musb_ep_program()
772 musb_write_txfunaddr(mbase, epnum, qh->addr_reg); in musb_ep_program()
773 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg); in musb_ep_program()
774 musb_write_txhubport(mbase, epnum, qh->h_port_reg); in musb_ep_program()
777 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg); in musb_ep_program()
781 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg); in musb_ep_program()
782 if (musb->double_buffer_not_ok) in musb_ep_program()
784 hw_ep->max_packet_sz_tx); in musb_ep_program()
785 else if (can_bulk_split(musb, qh->type)) in musb_ep_program()
787 | ((hw_ep->max_packet_sz_tx / in musb_ep_program()
788 packet_sz) - 1) << 11); in musb_ep_program()
791 qh->maxpacket | in musb_ep_program()
792 ((qh->hb_mult - 1) << 11)); in musb_ep_program()
793 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg); in musb_ep_program()
795 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg); in musb_ep_program()
796 if (musb->is_multipoint) in musb_ep_program()
798 qh->type_reg); in musb_ep_program()
801 if (can_bulk_split(musb, qh->type)) in musb_ep_program()
802 load_count = min((u32) hw_ep->max_packet_sz_tx, in musb_ep_program()
813 qh->segsize = load_count; in musb_ep_program()
817 /* re-enable interrupt */ in musb_ep_program()
824 if (hw_ep->rx_reinit) { in musb_ep_program()
828 if (usb_gettoggle(urb->dev, qh->epnum, 0)) in musb_ep_program()
833 if (qh->type == USB_ENDPOINT_XFER_INT) in musb_ep_program()
837 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
843 hw_ep->epnum, csr); in musb_ep_program()
853 dma_channel->actual_len = 0L; in musb_ep_program()
854 qh->segsize = len; in musb_ep_program()
857 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_ep_program()
858 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
864 dma_ok = dma_controller->channel_program(dma_channel, in musb_ep_program()
865 packet_sz, !(urb->transfer_flags & in musb_ep_program()
867 urb->transfer_dma + offset, in musb_ep_program()
868 qh->segsize); in musb_ep_program()
870 dma_controller->channel_release(dma_channel); in musb_ep_program()
871 hw_ep->rx_channel = dma_channel = NULL; in musb_ep_program()
877 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr); in musb_ep_program()
878 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_ep_program()
879 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
885 * Service the default endpoint (ep0) as host.
893 struct musb_hw_ep *hw_ep = musb->control_ep; in musb_h_ep0_continue()
894 struct musb_qh *qh = hw_ep->in_qh; in musb_h_ep0_continue()
897 switch (musb->ep0_stage) { in musb_h_ep0_continue()
899 fifo_dest = urb->transfer_buffer + urb->actual_length; in musb_h_ep0_continue()
900 fifo_count = min_t(size_t, len, urb->transfer_buffer_length - in musb_h_ep0_continue()
901 urb->actual_length); in musb_h_ep0_continue()
903 urb->status = -EOVERFLOW; in musb_h_ep0_continue()
907 urb->actual_length += fifo_count; in musb_h_ep0_continue()
908 if (len < qh->maxpacket) { in musb_h_ep0_continue()
912 } else if (urb->actual_length < in musb_h_ep0_continue()
913 urb->transfer_buffer_length) in musb_h_ep0_continue()
917 request = (struct usb_ctrlrequest *) urb->setup_packet; in musb_h_ep0_continue()
919 if (!request->wLength) { in musb_h_ep0_continue()
920 dev_dbg(musb->controller, "start no-DATA\n"); in musb_h_ep0_continue()
922 } else if (request->bRequestType & USB_DIR_IN) { in musb_h_ep0_continue()
923 dev_dbg(musb->controller, "start IN-DATA\n"); in musb_h_ep0_continue()
924 musb->ep0_stage = MUSB_EP0_IN; in musb_h_ep0_continue()
928 dev_dbg(musb->controller, "start OUT-DATA\n"); in musb_h_ep0_continue()
929 musb->ep0_stage = MUSB_EP0_OUT; in musb_h_ep0_continue()
934 fifo_count = min_t(size_t, qh->maxpacket, in musb_h_ep0_continue()
935 urb->transfer_buffer_length - in musb_h_ep0_continue()
936 urb->actual_length); in musb_h_ep0_continue()
938 fifo_dest = (u8 *) (urb->transfer_buffer in musb_h_ep0_continue()
939 + urb->actual_length); in musb_h_ep0_continue()
940 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n", in musb_h_ep0_continue()
946 urb->actual_length += fifo_count; in musb_h_ep0_continue()
950 default: in musb_h_ep0_continue()
951 ERR("bogus ep0 stage %d\n", musb->ep0_stage); in musb_h_ep0_continue()
959 * Handle default endpoint interrupt as host. Only called in IRQ time
969 void __iomem *mbase = musb->mregs; in musb_h_ep0_irq()
970 struct musb_hw_ep *hw_ep = musb->control_ep; in musb_h_ep0_irq()
971 void __iomem *epio = hw_ep->regs; in musb_h_ep0_irq()
972 struct musb_qh *qh = hw_ep->in_qh; in musb_h_ep0_irq()
985 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n", in musb_h_ep0_irq()
986 csr, qh, len, urb, musb->ep0_stage); in musb_h_ep0_irq()
989 if (MUSB_EP0_STATUS == musb->ep0_stage) { in musb_h_ep0_irq()
996 dev_dbg(musb->controller, "STALLING ENDPOINT\n"); in musb_h_ep0_irq()
997 status = -EPIPE; in musb_h_ep0_irq()
1000 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr); in musb_h_ep0_irq()
1001 status = -EPROTO; in musb_h_ep0_irq()
1004 dev_dbg(musb->controller, "control NAK timeout\n"); in musb_h_ep0_irq()
1011 * if (qh->ring.next != &musb->control), then in musb_h_ep0_irq()
1019 dev_dbg(musb->controller, "aborting\n"); in musb_h_ep0_irq()
1022 urb->status = status; in musb_h_ep0_irq()
1054 csr = (MUSB_EP0_IN == musb->ep0_stage) in musb_h_ep0_irq()
1058 if (usb_pipeout(urb->pipe) in musb_h_ep0_irq()
1059 || !urb->transfer_buffer_length) in musb_h_ep0_irq()
1067 musb->ep0_stage = MUSB_EP0_STATUS; in musb_h_ep0_irq()
1069 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr); in musb_h_ep0_irq()
1075 musb->ep0_stage = MUSB_EP0_IDLE; in musb_h_ep0_irq()
1088 submit_urb ->
1089 - if queue was empty, Program Endpoint
1090 - ... which starts DMA to fifo in mode 1 or 0
1092 DMA Isr (transfer complete) -> TxAvail()
1093 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1095 - TxPktRdy has to be set in mode 0 or for
1096 short packets in mode 1.
1101 /* Service a Tx-Available or dma completion irq for the endpoint */
1109 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_host_tx()
1110 void __iomem *epio = hw_ep->regs; in musb_host_tx()
1111 struct musb_qh *qh = hw_ep->out_qh; in musb_host_tx()
1114 void __iomem *mbase = musb->mregs; in musb_host_tx()
1123 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); in musb_host_tx()
1127 pipe = urb->pipe; in musb_host_tx()
1128 dma = is_dma_capable() ? hw_ep->tx_channel : NULL; in musb_host_tx()
1129 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, in musb_host_tx()
1135 dev_dbg(musb->controller, "TX end %d stall\n", epnum); in musb_host_tx()
1138 status = -EPIPE; in musb_host_tx()
1141 /* (NON-ISO) dma was disabled, fifo flushed */ in musb_host_tx()
1142 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum); in musb_host_tx()
1144 status = -ETIMEDOUT; in musb_host_tx()
1147 dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum); in musb_host_tx()
1154 * if (bulk && qh->ring.next != &musb->out_bulk), then in musb_host_tx()
1166 dma->status = MUSB_DMA_STATUS_CORE_ABORT; in musb_host_tx()
1167 (void) musb->dma_controller->channel_abort(dma); in musb_host_tx()
1192 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); in musb_host_tx()
1198 * DMA has completed. But if we're using DMA mode 1 (multi in musb_host_tx()
1202 * switch back to mode 0 to get that interrupt; we'll come in musb_host_tx()
1210 * it being 0 at this moment -- DMA interrupt latency in musb_host_tx()
1213 * programmer's guide... :-) in musb_host_tx()
1216 * in order not to re-trigger the packet send (this bit in musb_host_tx()
1219 * double-buffered FIFO mode, so we do an extra TXCSR in musb_host_tx()
1238 * Re-read TXCSR as we have spoiled its previous value. in musb_host_tx()
1246 * only if the FIFO still has data -- that should prevent the in musb_host_tx()
1247 * "missed" TXPKTRDY interrupts and deal with double-buffered in musb_host_tx()
1248 * FIFO mode too... in musb_host_tx()
1251 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, " in musb_host_tx()
1259 length = dma->actual_len; in musb_host_tx()
1261 length = qh->segsize; in musb_host_tx()
1262 qh->offset += length; in musb_host_tx()
1268 d = urb->iso_frame_desc + qh->iso_idx; in musb_host_tx()
1269 d->actual_length = length; in musb_host_tx()
1270 d->status = status; in musb_host_tx()
1271 if (++qh->iso_idx >= urb->number_of_packets) { in musb_host_tx()
1275 offset = d->offset; in musb_host_tx()
1276 length = d->length; in musb_host_tx()
1279 } else if (dma && urb->transfer_buffer_length == qh->offset) { in musb_host_tx()
1283 if (qh->segsize < qh->maxpacket) in musb_host_tx()
1285 else if (qh->offset == urb->transfer_buffer_length in musb_host_tx()
1286 && !(urb->transfer_flags in musb_host_tx()
1290 offset = qh->offset; in musb_host_tx()
1291 length = urb->transfer_buffer_length - offset; in musb_host_tx()
1297 /* urb->status != -EINPROGRESS means request has been faulted, in musb_host_tx()
1300 if (urb->status != -EINPROGRESS) { in musb_host_tx()
1303 status = urb->status; in musb_host_tx()
1308 urb->status = status; in musb_host_tx()
1309 urb->actual_length = qh->offset; in musb_host_tx()
1313 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb, in musb_host_tx()
1320 dev_dbg(musb->controller, "not complete, but DMA enabled?\n"); in musb_host_tx()
1327 * REVISIT: some docs say that when hw_ep->tx_double_buffered, in musb_host_tx()
1328 * (and presumably, FIFO is not half-full) we should write *two* in musb_host_tx()
1331 if (length > qh->maxpacket) in musb_host_tx()
1332 length = qh->maxpacket; in musb_host_tx()
1335 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset); in musb_host_tx()
1336 qh->segsize = length; in musb_host_tx()
1347 submit_urb ->
1348 - if queue was empty, ProgramEndpoint
1349 - first IN token is sent out (by setting ReqPkt)
1350 LinuxIsr -> RxReady()
1352 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1353 | -> DMA Isr (transfer complete) -> RxReady()
1354 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1355 | - if urb not complete, send next IN token (ReqPkt)
1358 ---------------------------
1360 * Nuances of mode 1:
1365 * difficult. Hence mode 1 is not used.
1372 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1374 * - overflow (full, PLUS more bytes in the terminal packet)
1376 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1377 * thus be a great candidate for using mode 1 ... for all but the
1383 /* Schedule next QH from musb->in_bulk and move the current qh to
1390 void __iomem *mbase = musb->mregs; in musb_bulk_rx_nak_timeout()
1391 void __iomem *epio = ep->regs; in musb_bulk_rx_nak_timeout()
1395 musb_ep_select(mbase, ep->epnum); in musb_bulk_rx_nak_timeout()
1396 dma = is_dma_capable() ? ep->rx_channel : NULL; in musb_bulk_rx_nak_timeout()
1404 cur_qh = first_qh(&musb->in_bulk); in musb_bulk_rx_nak_timeout()
1408 dma->status = MUSB_DMA_STATUS_CORE_ABORT; in musb_bulk_rx_nak_timeout()
1409 musb->dma_controller->channel_abort(dma); in musb_bulk_rx_nak_timeout()
1410 urb->actual_length += dma->actual_len; in musb_bulk_rx_nak_timeout()
1411 dma->actual_len = 0L; in musb_bulk_rx_nak_timeout()
1416 list_move_tail(&cur_qh->ring, &musb->in_bulk); in musb_bulk_rx_nak_timeout()
1418 /* get the next qh from musb->in_bulk */ in musb_bulk_rx_nak_timeout()
1419 next_qh = first_qh(&musb->in_bulk); in musb_bulk_rx_nak_timeout()
1422 ep->rx_reinit = 1; in musb_bulk_rx_nak_timeout()
1429 * and high-bandwidth IN transfer cases.
1434 struct musb_hw_ep *hw_ep = musb->endpoints + epnum; in musb_host_rx()
1435 void __iomem *epio = hw_ep->regs; in musb_host_rx()
1436 struct musb_qh *qh = hw_ep->in_qh; in musb_host_rx()
1438 void __iomem *mbase = musb->mregs; in musb_host_rx()
1449 dma = is_dma_capable() ? hw_ep->rx_channel : NULL; in musb_host_rx()
1457 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least in musb_host_rx()
1461 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, in musb_host_rx()
1467 pipe = urb->pipe; in musb_host_rx()
1469 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n", in musb_host_rx()
1470 epnum, rx_csr, urb->actual_length, in musb_host_rx()
1471 dma ? dma->actual_len : 0); in musb_host_rx()
1476 dev_dbg(musb->controller, "RX end %d STALL\n", epnum); in musb_host_rx()
1479 status = -EPIPE; in musb_host_rx()
1482 dev_dbg(musb->controller, "end %d RX proto error\n", epnum); in musb_host_rx()
1484 status = -EPROTO; in musb_host_rx()
1489 if (USB_ENDPOINT_XFER_ISOC != qh->type) { in musb_host_rx()
1490 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum); in musb_host_rx()
1500 if (usb_pipebulk(urb->pipe) in musb_host_rx()
1501 && qh->mux == 1 in musb_host_rx()
1502 && !list_is_singular(&musb->in_bulk)) { in musb_host_rx()
1513 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum); in musb_host_rx()
1518 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n", in musb_host_rx()
1520 status = -EPROTO; in musb_host_rx()
1527 dma->status = MUSB_DMA_STATUS_CORE_ABORT; in musb_host_rx()
1528 (void) musb->dma_controller->channel_abort(dma); in musb_host_rx()
1529 xfer_len = dma->actual_len; in musb_host_rx()
1548 /* FIXME this is _way_ too much in-line logic for Mentor DMA */ in musb_host_rx()
1558 dma->status = MUSB_DMA_STATUS_CORE_ABORT; in musb_host_rx()
1559 (void) musb->dma_controller->channel_abort(dma); in musb_host_rx()
1560 xfer_len = dma->actual_len; in musb_host_rx()
1564 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr, in musb_host_rx()
1574 xfer_len = dma->actual_len; in musb_host_rx()
1580 musb_writew(hw_ep->regs, MUSB_RXCSR, val); in musb_host_rx()
1586 d = urb->iso_frame_desc + qh->iso_idx; in musb_host_rx()
1587 d->actual_length = xfer_len; in musb_host_rx()
1590 * for iso_frame_desc->length in musb_host_rx()
1592 if (d->status != -EILSEQ && d->status != -EOVERFLOW) in musb_host_rx()
1593 d->status = 0; in musb_host_rx()
1595 if (++qh->iso_idx >= urb->number_of_packets) in musb_host_rx()
1602 done = (urb->actual_length + xfer_len >= in musb_host_rx()
1603 urb->transfer_buffer_length in musb_host_rx()
1604 || dma->actual_len < qh->maxpacket); in musb_host_rx()
1614 dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum, in musb_host_rx()
1621 } else if (urb->status == -EINPROGRESS) { in musb_host_rx()
1624 status = -EPROTO; in musb_host_rx()
1647 dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n", in musb_host_rx()
1649 urb->transfer_dma in musb_host_rx()
1650 + urb->actual_length, in musb_host_rx()
1651 qh->offset, in musb_host_rx()
1652 urb->transfer_buffer_length); in musb_host_rx()
1654 c = musb->dma_controller; in musb_host_rx()
1660 d = urb->iso_frame_desc + qh->iso_idx; in musb_host_rx()
1663 d_status = -EILSEQ; in musb_host_rx()
1664 urb->error_count++; in musb_host_rx()
1666 if (rx_count > d->length) { in musb_host_rx()
1668 d_status = -EOVERFLOW; in musb_host_rx()
1669 urb->error_count++; in musb_host_rx()
1671 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\ in musb_host_rx()
1672 rx_count, d->length); in musb_host_rx()
1674 length = d->length; in musb_host_rx()
1677 d->status = d_status; in musb_host_rx()
1678 buf = urb->transfer_dma + d->offset; in musb_host_rx()
1681 buf = urb->transfer_dma + in musb_host_rx()
1682 urb->actual_length; in musb_host_rx()
1685 dma->desired_mode = 0; in musb_host_rx()
1687 /* because of the issue below, mode 1 will in musb_host_rx()
1690 if ((urb->transfer_flags & in musb_host_rx()
1692 && (urb->transfer_buffer_length - in musb_host_rx()
1693 urb->actual_length) in musb_host_rx()
1694 > qh->maxpacket) in musb_host_rx()
1695 dma->desired_mode = 1; in musb_host_rx()
1696 if (rx_count < hw_ep->max_packet_sz_rx) { in musb_host_rx()
1698 dma->desired_mode = 0; in musb_host_rx()
1700 length = urb->transfer_buffer_length; in musb_host_rx()
1704 /* Disadvantage of using mode 1: in musb_host_rx()
1710 * If you try to use mode 1 for (transfer_buffer_length - 512), and try in musb_host_rx()
1711 * to use the extra IN token to grab the last packet using mode 0, then in musb_host_rx()
1714 * such that it gets lost when RxCSR is re-set at the end of the mode 1 in musb_host_rx()
1716 * try to configure for mode 0 soon after the mode 1 transfer is in musb_host_rx()
1724 if (dma->desired_mode == 0) in musb_host_rx()
1731 if (qh->hb_mult == 1) in musb_host_rx()
1741 ret = c->channel_program( in musb_host_rx()
1742 dma, qh->maxpacket, in musb_host_rx()
1743 dma->desired_mode, buf, length); in musb_host_rx()
1746 c->channel_release(dma); in musb_host_rx()
1747 hw_ep->rx_channel = NULL; in musb_host_rx()
1763 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : ""); in musb_host_rx()
1768 urb->actual_length += xfer_len; in musb_host_rx()
1769 qh->offset += xfer_len; in musb_host_rx()
1771 if (urb->status == -EINPROGRESS) in musb_host_rx()
1772 urb->status = status; in musb_host_rx()
1797 if (qh->type == USB_ENDPOINT_XFER_CONTROL) { in musb_schedule()
1798 head = &musb->control; in musb_schedule()
1799 hw_ep = musb->control_ep; in musb_schedule()
1813 best_end = -1; in musb_schedule()
1815 for (epnum = 1, hw_ep = musb->endpoints + 1; in musb_schedule()
1816 epnum < musb->nr_endpoints; in musb_schedule()
1823 if (hw_ep == musb->bulk_ep) in musb_schedule()
1827 diff = hw_ep->max_packet_sz_rx; in musb_schedule()
1829 diff = hw_ep->max_packet_sz_tx; in musb_schedule()
1830 diff -= (qh->maxpacket * qh->hb_mult); in musb_schedule()
1846 hw_ep = musb->endpoints + epnum; in musb_schedule()
1847 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in); in musb_schedule()
1848 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE) in musb_schedule()
1850 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) && in musb_schedule()
1859 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) { in musb_schedule()
1860 hw_ep = musb->bulk_ep; in musb_schedule()
1862 head = &musb->in_bulk; in musb_schedule()
1864 head = &musb->out_bulk; in musb_schedule()
1873 if (is_in && qh->dev) in musb_schedule()
1874 qh->intv_reg = in musb_schedule()
1875 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4; in musb_schedule()
1878 return -ENOSPC; in musb_schedule()
1882 qh->mux = 0; in musb_schedule()
1883 hw_ep = musb->endpoints + best_end; in musb_schedule()
1884 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end); in musb_schedule()
1888 list_add_tail(&qh->ring, head); in musb_schedule()
1889 qh->mux = 1; in musb_schedule()
1891 qh->hw_ep = hw_ep; in musb_schedule()
1892 qh->hep->hcpriv = qh; in musb_schedule()
1902 if ((musb_readb(musb->mregs, MUSB_POWER) & MUSB_POWER_HSMODE) && in tt_needed()
1903 (dev->speed < USB_SPEED_HIGH)) in tt_needed()
1920 struct usb_host_endpoint *hep = urb->ep;
1922 struct usb_endpoint_descriptor *epd = &hep->desc;
1927 /* host role must be active */
1928 if (!is_host_active(musb) || !musb->is_active)
1929 return -ENODEV;
1931 spin_lock_irqsave(&musb->lock, flags);
1933 qh = ret ? NULL : hep->hcpriv;
1935 urb->hcpriv = qh;
1936 spin_unlock_irqrestore(&musb->lock, flags);
1939 * hep->urb_list now ... so we're done, unless hep wasn't yet
1942 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
1943 * disabled, testing for empty qh->ring and avoiding qh setup costs
1957 spin_lock_irqsave(&musb->lock, flags);
1959 spin_unlock_irqrestore(&musb->lock, flags);
1960 return -ENOMEM;
1963 qh->hep = hep;
1964 qh->dev = urb->dev;
1965 INIT_LIST_HEAD(&qh->ring);
1966 qh->is_ready = 1;
1968 qh->maxpacket = usb_endpoint_maxp(epd);
1969 qh->type = usb_endpoint_type(epd);
1975 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
1976 if (qh->hb_mult > 1) {
1977 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
1980 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
1981 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
1983 ret = -EMSGSIZE;
1986 qh->maxpacket &= 0x7ff;
1989 qh->epnum = usb_endpoint_num(epd);
1991 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
1992 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
1995 type_reg = (qh->type << 4) | qh->epnum;
1996 switch (urb->dev->speed) {
2003 default:
2006 qh->type_reg = type_reg;
2009 switch (qh->type) {
2015 if (urb->dev->speed <= USB_SPEED_FULL) {
2016 interval = max_t(u8, epd->bInterval, 1);
2022 interval = min_t(u8, epd->bInterval, 16);
2024 default:
2029 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
2041 qh->intv_reg = interval;
2044 if (musb->is_multipoint) {
2046 struct usb_device *parent = urb->dev->parent;
2048 struct usb_device *parent = usb_dev_get_parent(urb->dev);
2052 if (parent != hcd->self.root_hub) {
2056 qh->h_addr_reg = (u8) parent->devnum;
2060 if (urb->dev->tt) {
2061 qh->h_port_reg = (u8) urb->dev->ttport;
2062 if (urb->dev->tt->hub)
2063 qh->h_addr_reg =
2064 (u8) urb->dev->tt->hub->devnum;
2065 if (urb->dev->tt->multi)
2066 qh->h_addr_reg |= 0x80;
2069 if (tt_needed(musb, urb->dev)) {
2072 usb_find_usb2_hub_address_port(urb->dev,
2075 qh->h_addr_reg = hubaddr;
2076 qh->h_port_reg = portnr;
2082 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
2086 spin_lock_irqsave(&musb->lock, flags);
2087 if (hep->hcpriv) {
2096 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2099 urb->hcpriv = qh;
2100 /* FIXME set urb->start_frame for iso/intr, it's tested in
2104 spin_unlock_irqrestore(&musb->lock, flags);
2108 spin_lock_irqsave(&musb->lock, flags);
2110 spin_unlock_irqrestore(&musb->lock, flags);
2123 struct musb_hw_ep *ep = qh->hw_ep;
2124 struct musb *musb = ep->musb;
2125 void __iomem *epio = ep->regs;
2126 unsigned hw_end = ep->epnum;
2127 void __iomem *regs = ep->musb->mregs;
2128 int is_in = usb_pipein(urb->pipe);
2137 dma = is_in ? ep->rx_channel : ep->tx_channel;
2139 status = ep->musb->dma_controller->channel_abort(dma);
2140 dev_dbg(musb->controller,
2141 "abort %cX%d DMA for urb %p --> %d\n",
2142 is_in ? 'R' : 'T', ep->epnum,
2144 urb->actual_length += dma->actual_len;
2149 if (ep->epnum && is_in) {
2155 * clearing that status is platform-specific...
2157 } else if (ep->epnum) {
2175 musb_advance_schedule(ep->musb, urb, ep, is_in);
2191 int is_in = usb_pipein(urb->pipe);
2194 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
2195 usb_pipedevice(urb->pipe),
2196 usb_pipeendpoint(urb->pipe),
2199 spin_lock_irqsave(&musb->lock, flags);
2204 qh = urb->hcpriv;
2214 * Otherwise abort current transfer, pending DMA, etc.; urb->status
2218 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
2220 if (!qh->is_ready
2221 || urb->urb_list.prev != &qh->hep->urb_list
2222 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2223 int ready = qh->is_ready;
2225 qh->is_ready = 0;
2227 qh->is_ready = ready;
2232 if (ready && list_empty(&qh->hep->urb_list)) {
2233 qh->hep->hcpriv = NULL;
2234 list_del(&qh->ring);
2240 spin_unlock_irqrestore(&musb->lock, flags);
2249 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
2255 spin_lock_irqsave(&musb->lock, flags);
2257 qh = hep->hcpriv;
2261 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2264 qh->is_ready = 0;
2265 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2269 if (!urb->unlinked)
2270 urb->status = -ESHUTDOWN;
2278 while (!list_empty(&hep->urb_list)) {
2280 urb->status = -ESHUTDOWN;
2281 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2285 * other transfers, and since !qh->is_ready nothing
2288 while (!list_empty(&hep->urb_list))
2289 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2291 hep->hcpriv = NULL;
2292 list_del(&qh->ring);
2296 spin_unlock_irqrestore(&musb->lock, flags);
2303 return musb_readw(musb->mregs, MUSB_FRAME);
2313 hcd->state = HC_STATE_RUNNING;
2314 musb->port1_status = 0;
2321 hcd->state = HC_STATE_HALT;
2332 switch (musb->xceiv->state) {
2340 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2342 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2344 default:
2348 if (musb->is_active) {
2350 otg_state_string(musb->xceiv->state));
2351 return -EBUSY;
2363 .description = "musb-hcd",