Lines Matching full:csr
93 u16 csr; in musb_h_tx_flush_fifo() local
97 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
98 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { in musb_h_tx_flush_fifo()
99 if (csr != lastcsr) in musb_h_tx_flush_fifo()
100 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr); in musb_h_tx_flush_fifo()
101 lastcsr = csr; in musb_h_tx_flush_fifo()
102 csr |= MUSB_TXCSR_FLUSHFIFO; in musb_h_tx_flush_fifo()
103 musb_writew(epio, MUSB_TXCSR, csr); in musb_h_tx_flush_fifo()
104 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
106 "Could not flush host TX%d fifo: csr: %04x\n", in musb_h_tx_flush_fifo()
107 ep->epnum, csr)) in musb_h_tx_flush_fifo()
116 u16 csr; in musb_h_ep0_flush_fifo() local
121 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_ep0_flush_fifo()
122 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY))) in musb_h_ep0_flush_fifo()
125 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_ep0_flush_fifo()
129 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n", in musb_h_ep0_flush_fifo()
130 ep->epnum, csr); in musb_h_ep0_flush_fifo()
317 u16 csr; in musb_save_toggle() local
325 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE; in musb_save_toggle()
327 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE; in musb_save_toggle()
329 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0); in musb_save_toggle()
426 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr) in musb_h_flush_rxfifo() argument
432 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY; in musb_h_flush_rxfifo()
433 csr &= ~(MUSB_RXCSR_H_REQPKT in musb_h_flush_rxfifo()
438 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_h_flush_rxfifo()
439 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_h_flush_rxfifo()
453 u16 csr; in musb_host_packet_rx() local
530 csr = musb_readw(epio, MUSB_RXCSR); in musb_host_packet_rx()
531 csr |= MUSB_RXCSR_H_WZC_BITS; in musb_host_packet_rx()
533 musb_h_flush_rxfifo(hw_ep, csr); in musb_host_packet_rx()
536 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT); in musb_host_packet_rx()
538 csr |= MUSB_RXCSR_H_REQPKT; in musb_host_packet_rx()
539 musb_writew(epio, MUSB_RXCSR, csr); in musb_host_packet_rx()
546 * when we do, use tx/rx reinit routine and then construct a new CSR
556 u16 csr; in musb_rx_reinit() local
565 csr = musb_readw(ep->regs, MUSB_TXCSR); in musb_rx_reinit()
566 if (csr & MUSB_TXCSR_MODE) { in musb_rx_reinit()
568 csr = musb_readw(ep->regs, MUSB_TXCSR); in musb_rx_reinit()
570 csr | MUSB_TXCSR_FRCDATATOG); in musb_rx_reinit()
577 if (csr & MUSB_TXCSR_DMAMODE) in musb_rx_reinit()
583 csr = musb_readw(ep->regs, MUSB_RXCSR); in musb_rx_reinit()
584 if (csr & MUSB_RXCSR_RXPKTRDY) in musb_rx_reinit()
623 u16 csr; in musb_tx_dma_program() local
630 csr = musb_readw(epio, MUSB_TXCSR); in musb_tx_dma_program()
633 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB; in musb_tx_dma_program()
636 csr |= MUSB_TXCSR_AUTOSET; in musb_tx_dma_program()
639 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE); in musb_tx_dma_program()
640 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */ in musb_tx_dma_program()
643 musb_writew(epio, MUSB_TXCSR, csr); in musb_tx_dma_program()
670 csr = musb_readw(epio, MUSB_TXCSR); in musb_tx_dma_program()
671 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB); in musb_tx_dma_program()
672 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS); in musb_tx_dma_program()
724 u16 csr; in musb_ep_program() local
728 csr = musb_readw(epio, MUSB_TXCSR); in musb_ep_program()
744 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT in musb_ep_program()
752 csr |= MUSB_TXCSR_MODE; in musb_ep_program()
755 csr |= MUSB_TXCSR_H_WR_DATATOGGLE in musb_ep_program()
758 csr |= MUSB_TXCSR_CLRDATATOG; in musb_ep_program()
760 musb_writew(epio, MUSB_TXCSR, csr); in musb_ep_program()
762 csr &= ~MUSB_TXCSR_DMAMODE; in musb_ep_program()
763 musb_writew(epio, MUSB_TXCSR, csr); in musb_ep_program()
764 csr = musb_readw(epio, MUSB_TXCSR); in musb_ep_program()
822 u16 csr; in musb_ep_program() local
829 csr = MUSB_RXCSR_H_WR_DATATOGGLE in musb_ep_program()
832 csr = 0; in musb_ep_program()
834 csr |= MUSB_RXCSR_DISNYET; in musb_ep_program()
837 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
839 if (csr & (MUSB_RXCSR_RXPKTRDY in musb_ep_program()
842 ERR("broken !rx_reinit, ep%d csr %04x\n", in musb_ep_program()
843 hw_ep->epnum, csr); in musb_ep_program()
846 csr &= MUSB_RXCSR_DISNYET; in musb_ep_program()
857 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_ep_program()
858 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
873 csr |= MUSB_RXCSR_DMAENAB; in musb_ep_program()
876 csr |= MUSB_RXCSR_H_REQPKT; in musb_ep_program()
877 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr); in musb_ep_program()
878 musb_writew(hw_ep->regs, MUSB_RXCSR, csr); in musb_ep_program()
879 csr = musb_readw(hw_ep->regs, MUSB_RXCSR); in musb_ep_program()
967 u16 csr, len; in musb_h_ep0_irq() local
980 csr = musb_readw(epio, MUSB_CSR0); in musb_h_ep0_irq()
981 len = (csr & MUSB_CSR0_RXPKTRDY) in musb_h_ep0_irq()
986 csr, qh, len, urb, musb->ep0_stage); in musb_h_ep0_irq()
995 if (csr & MUSB_CSR0_H_RXSTALL) { in musb_h_ep0_irq()
999 } else if (csr & MUSB_CSR0_H_ERROR) { in musb_h_ep0_irq()
1000 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr); in musb_h_ep0_irq()
1003 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) { in musb_h_ep0_irq()
1026 if (csr & MUSB_CSR0_H_REQPKT) { in musb_h_ep0_irq()
1027 csr &= ~MUSB_CSR0_H_REQPKT; in musb_h_ep0_irq()
1028 musb_writew(epio, MUSB_CSR0, csr); in musb_h_ep0_irq()
1029 csr &= ~MUSB_CSR0_H_NAKTIMEOUT; in musb_h_ep0_irq()
1030 musb_writew(epio, MUSB_CSR0, csr); in musb_h_ep0_irq()
1054 csr = (MUSB_EP0_IN == musb->ep0_stage) in musb_h_ep0_irq()
1060 csr = MUSB_CSR0_H_STATUSPKT in musb_h_ep0_irq()
1063 csr = MUSB_CSR0_H_STATUSPKT in musb_h_ep0_irq()
1069 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr); in musb_h_ep0_irq()
1072 musb_writew(epio, MUSB_CSR0, csr); in musb_h_ep0_irq()
1123 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); in musb_host_tx()
1129 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr, in musb_host_tx()
1192 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr); in musb_host_tx()
1252 "CSR %04x\n", tx_csr); in musb_host_tx()
1461 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val, in musb_host_rx()
1539 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr); in musb_host_rx()
2130 u16 csr; local
2151 csr = musb_h_flush_rxfifo(ep, 0);
2159 csr = musb_readw(epio, MUSB_TXCSR);
2160 csr &= ~(MUSB_TXCSR_AUTOSET
2166 musb_writew(epio, MUSB_TXCSR, csr);
2168 musb_writew(epio, MUSB_TXCSR, csr);
2170 csr = musb_readw(epio, MUSB_TXCSR);