Lines Matching refs:MUSB_CSR0
512 musb_writew(regs, MUSB_CSR0, csr); in ep0_rxstate()
532 dev_dbg(musb->controller, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0)); in ep0_txstate()
556 musb_writew(regs, MUSB_CSR0, csr); in ep0_txstate()
617 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY); in musb_read_setup()
618 while ((musb_readw(regs, MUSB_CSR0) in musb_read_setup()
654 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_irq()
672 musb_writew(regs, MUSB_CSR0, in musb_g_ep0_irq()
676 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_irq()
681 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND); in musb_g_ep0_irq()
695 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_irq()
869 musb_writew(regs, MUSB_CSR0, in musb_g_ep0_irq()
886 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL); in musb_g_ep0_irq()
970 musb_writew(regs, MUSB_CSR0, in musb_g_ep0_queue()
981 musb_writew(regs, MUSB_CSR0, musb->ackpend); in musb_g_ep0_queue()
1032 csr = musb_readw(regs, MUSB_CSR0); in musb_g_ep0_halt()
1042 musb_writew(regs, MUSB_CSR0, csr); in musb_g_ep0_halt()