1 // SPDX-License-Identifier: GPL-2.0+
5  * FSL USB HOST xHCI Controller
11 #include <usb.h>
14 #include <linux/usb/xhci-fsl.h>
15 #include <linux/usb/dwc3.h>
61 	clrsetbits_le32(&dwc3_reg->g_sbuscfg0, USB3_ENABLE_BEAT_BURST_MASK,  in fsl_xhci_set_beat_burst_length()
63 	setbits_le32(&dwc3_reg->g_sbuscfg1, USB3_SET_BEAT_BURST_LIMIT);  in fsl_xhci_set_beat_burst_length()
70 	ret = dwc3_core_init(fsl_xhci->dwc3_reg);  in fsl_xhci_core_init()
76 	/* We are hard-coding DWC3 core to Host Mode */  in fsl_xhci_core_init()
77 	dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);  in fsl_xhci_core_init()
80 	dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);  in fsl_xhci_core_init()
83 	fsl_xhci_set_beat_burst_length(fsl_xhci->dwc3_reg);  in fsl_xhci_core_init()
86 	 * A-010151: The dwc3 phy TSMC 28-nm HPM 0.9/1.8 V does not  in fsl_xhci_core_init()
87 	 * reliably support Rx Detect in P3 mode(P3 is the default  in fsl_xhci_core_init()
89 	 * reliably in Super Speed mode. So, USB controller to configure  in fsl_xhci_core_init()
90 	 * USB in P2 mode whenever the Receive Detect feature is required.  in fsl_xhci_core_init()
91 	 * whenever the Receive Detect feature is required.  in fsl_xhci_core_init()
94 		clrsetbits_le32(&fsl_xhci->dwc3_reg->g_usb3pipectl[0],  in fsl_xhci_core_init()
122 	priv->hcd_base = devfdt_get_addr(dev);  in xhci_fsl_probe()
123 	if (priv->hcd_base == FDT_ADDR_T_NONE) {  in xhci_fsl_probe()
125 		return -ENXIO;  in xhci_fsl_probe()
127 	priv->ctx.hcd = (struct xhci_hccr *)priv->hcd_base;  in xhci_fsl_probe()
128 	priv->ctx.dwc3_reg = (struct dwc3 *)((char *)(priv->hcd_base) +  in xhci_fsl_probe()
133 	ret = fsl_xhci_core_init(&priv->ctx);  in xhci_fsl_probe()
139 	hccr = (struct xhci_hccr *)(priv->ctx.hcd);  in xhci_fsl_probe()
141 				+ HC_LENGTH(xhci_readl(&hccr->cr_capbase)));  in xhci_fsl_probe()
143 	debug("xhci-fsl: init hccr %lx and hcor %lx hc_length %lx\n",  in xhci_fsl_probe()
145 	      (uintptr_t)HC_LENGTH(xhci_readl(&hccr->cr_capbase)));  in xhci_fsl_probe()
154 	fsl_xhci_core_exit(&priv->ctx);  in xhci_fsl_remove()
160 	{ .compatible = "fsl,layerscape-dwc3", },
181 	ctx->hcd = (struct xhci_hccr *)ctr_addr[index];  in xhci_hcd_init()
182 	ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);  in xhci_hcd_init()
186 		puts("Failed to initialize board for USB\n");  in xhci_hcd_init()
198 	*hccr = (struct xhci_hccr *)ctx->hcd;  in xhci_hcd_init()
200 				+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));  in xhci_hcd_init()
202 	debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n",  in xhci_hcd_init()
204 	      (uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));  in xhci_hcd_init()