usb/host/xhci-dwc3.c

1 // SPDX-License-Identifier: GPL-2.0+
13 #include <generic-phy.h>
15 #include <dwc3-uboot.h>
27 void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)  in dwc3_set_mode()  argument
29 	clrsetbits_le32(&dwc3_reg->g_ctl,  in dwc3_set_mode()
31 			DWC3_GCTL_PRTCAPDIR(mode));  in dwc3_set_mode()
37 	setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);  in dwc3_phy_reset()
40 	setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);  in dwc3_phy_reset()
45 	clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);  in dwc3_phy_reset()
48 	clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);  in dwc3_phy_reset()
54 	setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);  in dwc3_core_soft_reset()
56 	/* reset USB3 phy - if required */  in dwc3_core_soft_reset()
62 	clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);  in dwc3_core_soft_reset()
71 	revision = readl(&dwc3_reg->g_snpsid);  in dwc3_core_init()
75 		return -1;  in dwc3_core_init()
80 	dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);  in dwc3_core_init()
82 	reg = readl(&dwc3_reg->g_ctl);  in dwc3_core_init()
85 	switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {  in dwc3_core_init()
89 	default:  in dwc3_core_init()
96 	 * and falls back to high-speed mode which causes  in dwc3_core_init()
102 	writel(reg, &dwc3_reg->g_ctl);  in dwc3_core_init()
109 	setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |  in dwc3_set_fladj()
125 			HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));  in xhci_dwc3_probe()
127 	ret = dwc3_setup_phy(dev, &plat->usb_phys, &plat->num_phys);  in xhci_dwc3_probe()
128 	if (ret && (ret != -ENOTSUPP))  in xhci_dwc3_probe()
137 		/* by default set dual role mode to HOST */  in xhci_dwc3_probe()
149 	dwc3_shutdown_phy(dev, plat->usb_phys, plat->num_phys);  in xhci_dwc3_remove()
160 	.name = "xhci-dwc3",