Lines Matching +full:vbus +full:- +full:divider
1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (c) 2009-2015 NVIDIA Corporation
12 #include <asm-generic/gpio.h>
14 #include <asm/arch-tegra/usb.h>
15 #include <asm/arch-tegra/clk_rst.h>
36 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */
37 PARAM_DIVM, /* PLL INPUT DIVIDER */
38 PARAM_DIVP, /* POST DIVIDER (2^N) */
41 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
42 PARAM_STABLE_COUNT, /* PLL-U STABLE count */
43 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
44 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
80 struct gpio_desc vbus_gpio; /* GPIO for vbus enable */
89 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
92 * ----------------------------------------------------------------------
102 * ---------------------------------------------------------------------------
114 * 0xffff -> No debouncing at all
208 struct fdt_usb *config = ctrl->priv; in tegra_ehci_powerup_fixup()
211 controller = &fdt_usb_controllers[config->type]; in tegra_ehci_powerup_fixup()
213 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */ in tegra_ehci_powerup_fixup()
214 if (controller->has_hostpc) in tegra_ehci_powerup_fixup()
217 if (!config->has_legacy_mode) in tegra_ehci_powerup_fixup()
226 struct fdt_usb *config = ctrl->priv; in tegra_ehci_set_usbmode()
230 usbctlr = config->reg; in tegra_ehci_set_usbmode()
232 tmp = ehci_readl(&usbctlr->usb_mode); in tegra_ehci_set_usbmode()
234 ehci_writel(&usbctlr->usb_mode, tmp); in tegra_ehci_set_usbmode()
239 struct fdt_usb *config = ctrl->priv; in tegra_ehci_get_port_speed()
244 controller = &fdt_usb_controllers[config->type]; in tegra_ehci_get_port_speed()
245 if (controller->has_hostpc) { in tegra_ehci_get_port_speed()
246 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + in tegra_ehci_get_port_speed()
254 /* Set up VBUS for host/device mode */
259 * check if remote host is driving VBus and bail out in this case. in set_up_vbus()
262 config->dr_mode == DR_MODE_OTG && in set_up_vbus()
263 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) { in set_up_vbus()
264 printf("tegrausb: VBUS input active; not enabling as host\n"); in set_up_vbus()
268 if (dm_gpio_is_valid(&config->vbus_gpio)) { in set_up_vbus()
272 dm_gpio_set_value(&config->vbus_gpio, vbus_value); in set_up_vbus()
275 gpio_get_number(&config->vbus_gpio), vbus_value); in set_up_vbus()
283 reset_periph(config->periph_id, 2); in usbf_reset_controller()
289 if (config->has_legacy_mode) in usbf_reset_controller()
290 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE); in usbf_reset_controller()
293 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); in usbf_reset_controller()
296 if (config->utmi) in usbf_reset_controller()
297 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB); in usbf_reset_controller()
304 timing = controller->pll_parameter + in get_pll_timing()
314 struct usb_ctlr *usbctlr = config->reg; in init_phy_mux()
317 if (config->periph_id == PERIPH_ID_USBD) { in init_phy_mux()
318 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK, in init_phy_mux()
320 clrbits_le32(&usbctlr->port_sc1, STS1); in init_phy_mux()
322 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, in init_phy_mux()
324 clrbits_le32(&usbctlr->port_sc1, STS); in init_phy_mux()
328 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC, in init_phy_mux()
335 * already made at reset time, so this write is a no-op. in init_phy_mux()
337 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK, in init_phy_mux()
339 clrbits_le32(&usbctlr->hostpc1_devlc, STS); in init_phy_mux()
351 struct usb_ctlr *usbctlr = config->reg; in init_utmi_usb_controller()
355 clock_enable(config->periph_id); in init_utmi_usb_controller()
361 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); in init_utmi_usb_controller()
367 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask, in init_utmi_usb_controller()
374 if (config->dr_mode == DR_MODE_OTG && in init_utmi_usb_controller()
375 dm_gpio_is_valid(&config->vbus_gpio)) in init_utmi_usb_controller()
376 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, in init_utmi_usb_controller()
380 controller = &fdt_usb_controllers[config->type]; in init_utmi_usb_controller()
381 debug("controller=%p, type=%d\n", controller, config->type); in init_utmi_usb_controller()
389 if (!controller->has_hostpc) { in init_utmi_usb_controller()
390 val = readl(&usbctlr->utmip_misc_cfg1); in init_utmi_usb_controller()
397 writel(val, &usbctlr->utmip_misc_cfg1); in init_utmi_usb_controller()
400 val = readl(&usbctlr->utmip_pll_cfg1); in init_utmi_usb_controller()
407 writel(val, &usbctlr->utmip_pll_cfg1); in init_utmi_usb_controller()
411 val = readl(&clkrst->crc_utmip_pll_cfg2); in init_utmi_usb_controller()
418 writel(val, &clkrst->crc_utmip_pll_cfg2); in init_utmi_usb_controller()
421 val = readl(&clkrst->crc_utmip_pll_cfg1); in init_utmi_usb_controller()
428 writel(val, &clkrst->crc_utmip_pll_cfg1); in init_utmi_usb_controller()
431 clrbits_le32(&clkrst->crc_utmip_pll_cfg1, in init_utmi_usb_controller()
436 val = readl(&usbctlr->utmip_xcvr_cfg0); in init_utmi_usb_controller()
443 writel(val, &usbctlr->utmip_xcvr_cfg0); in init_utmi_usb_controller()
444 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, in init_utmi_usb_controller()
449 if (config->periph_id != PERIPH_ID_USBD) { in init_utmi_usb_controller()
455 ((unsigned long)config->reg & USB1_ADDR_MASK); in init_utmi_usb_controller()
456 val = readl(&usb1ctlr->utmip_bias_cfg0); in init_utmi_usb_controller()
462 writel(val, &usb1ctlr->utmip_bias_cfg0); in init_utmi_usb_controller()
465 clrbits_le32(&usbctlr->utmip_misc_cfg0, in init_utmi_usb_controller()
470 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, in init_utmi_usb_controller()
474 /* Program debounce time for VBUS to become valid */ in init_utmi_usb_controller()
475 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, in init_utmi_usb_controller()
480 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, in init_utmi_usb_controller()
484 clrsetbits_le32(&usbctlr->utmip_bias_cfg1, in init_utmi_usb_controller()
489 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); in init_utmi_usb_controller()
492 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); in init_utmi_usb_controller()
494 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); in init_utmi_usb_controller()
495 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); in init_utmi_usb_controller()
507 val = readl(&usbctlr->utmip_hsrx_cfg0); in init_utmi_usb_controller()
512 writel(val, &usbctlr->utmip_hsrx_cfg0); in init_utmi_usb_controller()
515 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, in init_utmi_usb_controller()
523 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); in init_utmi_usb_controller()
525 if (controller->has_hostpc) { in init_utmi_usb_controller()
526 if (config->periph_id == PERIPH_ID_USBD) in init_utmi_usb_controller()
527 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, in init_utmi_usb_controller()
529 if (config->periph_id == PERIPH_ID_USB2) in init_utmi_usb_controller()
530 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, in init_utmi_usb_controller()
532 if (config->periph_id == PERIPH_ID_USB3) in init_utmi_usb_controller()
533 clrbits_le32(&clkrst->crc_utmip_pll_cfg2, in init_utmi_usb_controller()
536 /* Finished the per-controller init. */ in init_utmi_usb_controller()
538 /* De-assert UTMIP_RESET to bring out of reset. */ in init_utmi_usb_controller()
539 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); in init_utmi_usb_controller()
542 for (loop_count = 100000; loop_count != 0; loop_count--) { in init_utmi_usb_controller()
543 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) in init_utmi_usb_controller()
548 return -ETIMEDOUT; in init_utmi_usb_controller()
551 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); in init_utmi_usb_controller()
557 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | in init_utmi_usb_controller()
559 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | in init_utmi_usb_controller()
562 if (controller->has_hostpc) { in init_utmi_usb_controller()
568 ((unsigned long)config->reg & USB1_ADDR_MASK); in init_utmi_usb_controller()
569 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); in init_utmi_usb_controller()
571 clrbits_le32(&usb1ctlr->utmip_bias_cfg1, in init_utmi_usb_controller()
590 struct usb_ctlr *usbctlr = config->reg; in init_ulpi_usb_controller()
598 if (dm_gpio_is_valid(&config->phy_reset_gpio)) { in init_ulpi_usb_controller()
600 * This GPIO is typically active-low, and marked as such in in init_ulpi_usb_controller()
605 * and the second call logically de-asserts the reset signal, in init_ulpi_usb_controller()
608 dm_gpio_set_value(&config->phy_reset_gpio, 1); in init_ulpi_usb_controller()
610 dm_gpio_set_value(&config->phy_reset_gpio, 0); in init_ulpi_usb_controller()
614 clock_enable(config->periph_id); in init_ulpi_usb_controller()
618 setbits_le32(&usbctlr->ulpi_timing_ctrl_0, in init_ulpi_usb_controller()
625 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); in init_ulpi_usb_controller()
629 writel(val, &usbctlr->ulpi_timing_ctrl_1); in init_ulpi_usb_controller()
634 writel(val, &usbctlr->ulpi_timing_ctrl_1); in init_ulpi_usb_controller()
640 writel(val, &usbctlr->ulpi_timing_ctrl_1); in init_ulpi_usb_controller()
642 /* set up phy for host operation with external vbus supply */ in init_ulpi_usb_controller()
644 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; in init_ulpi_usb_controller()
656 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); in init_ulpi_usb_controller()
659 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); in init_ulpi_usb_controller()
660 for (loop_count = 100000; loop_count != 0; loop_count--) { in init_ulpi_usb_controller()
661 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) in init_ulpi_usb_controller()
666 return -ETIMEDOUT; in init_ulpi_usb_controller()
667 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); in init_ulpi_usb_controller()
677 return -ENOSYS; in init_ulpi_usb_controller()
696 config->reg = (struct usb_ctlr *)dev_read_addr(dev); in fdt_decode_usb()
697 debug("reg=%p\n", config->reg); in fdt_decode_usb()
701 config->dr_mode = DR_MODE_HOST; in fdt_decode_usb()
703 config->dr_mode = DR_MODE_DEVICE; in fdt_decode_usb()
705 config->dr_mode = DR_MODE_OTG; in fdt_decode_usb()
709 return -EINVAL; in fdt_decode_usb()
712 config->dr_mode = DR_MODE_HOST; in fdt_decode_usb()
716 config->utmi = phy && 0 == strcmp("utmi", phy); in fdt_decode_usb()
717 config->ulpi = phy && 0 == strcmp("ulpi", phy); in fdt_decode_usb()
718 config->has_legacy_mode = dev_read_bool(dev, "nvidia,has-legacy-mode"); in fdt_decode_usb()
719 config->periph_id = clock_decode_periph_id(dev); in fdt_decode_usb()
720 if (config->periph_id == PERIPH_ID_NONE) { in fdt_decode_usb()
722 return -EINVAL; in fdt_decode_usb()
724 gpio_request_by_name(dev, "nvidia,vbus-gpio", 0, &config->vbus_gpio, in fdt_decode_usb()
726 gpio_request_by_name(dev, "nvidia,phy-reset-gpio", 0, in fdt_decode_usb()
727 &config->phy_reset_gpio, GPIOD_IS_OUT); in fdt_decode_usb()
728 …debug("legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, vbus=%d, phy_reset=%d, dr_mode=%d, reg=%p\n… in fdt_decode_usb()
729 config->has_legacy_mode, config->utmi, config->ulpi, in fdt_decode_usb()
730 config->periph_id, gpio_get_number(&config->vbus_gpio), in fdt_decode_usb()
731 gpio_get_number(&config->phy_reset_gpio), config->dr_mode, in fdt_decode_usb()
732 config->reg); in fdt_decode_usb()
743 switch (config->dr_mode) { in usb_common_init()
749 config->dr_mode); in usb_common_init()
750 return -1; in usb_common_init()
754 if (config->periph_id != PERIPH_ID_USBD) { in usb_common_init()
756 return -1; in usb_common_init()
758 if (!config->utmi) { in usb_common_init()
760 return -1; in usb_common_init()
762 switch (config->dr_mode) { in usb_common_init()
768 config->dr_mode); in usb_common_init()
769 return -1; in usb_common_init()
774 return -1; in usb_common_init()
777 debug("%d, %d\n", config->utmi, config->ulpi); in usb_common_init()
778 if (config->utmi) in usb_common_init()
780 else if (config->ulpi) in usb_common_init()
787 config->init_type = init; in usb_common_init()
796 usbctlr = priv->reg; in usb_common_uninit()
799 writel(0, &usbctlr->usb_cmd); in usb_common_uninit()
803 writel(2, &usbctlr->usb_cmd); in usb_common_uninit()
822 priv->type = dev_get_driver_data(dev); in ehci_usb_ofdata_to_platdata()
836 ret = usb_common_init(priv, plat->init_type); in ehci_usb_probe()
839 hccr = (struct ehci_hccr *)&priv->reg->cap_length; in ehci_usb_probe()
840 hcor = (struct ehci_hcor *)&priv->reg->usb_cmd; in ehci_usb_probe()
842 config_clock(get_pll_timing(&fdt_usb_controllers[priv->type])); in ehci_usb_probe()
847 plat->init_type); in ehci_usb_probe()
851 { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 },
852 { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 },
853 { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 },
854 { .compatible = "nvidia,tegra210-ehci", .data = USB_CTLR_T210 },