100  * Endpoint FIFO CSR bits have a mix of bits, making it unsafe to just write
125 	u32		csr;  in read_fifo()  local
137 	csr = __raw_readl(creg);  in read_fifo()
138 	if ((csr & RX_DATA_READY) == 0)  in read_fifo()
141 	count = (csr & AT91_UDP_RXBYTECNT) >> 16;  in read_fifo()
152 	csr |= CLR_FX;  in read_fifo()
155 			csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0);  in read_fifo()
158 			csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK1);  in read_fifo()
162 		csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0);  in read_fifo()
163 	__raw_writel(csr, creg);  in read_fifo()
182 		 * CSR returns bad RXCOUNT when read too soon after updating  in read_fifo()
185 		csr = __raw_readl(creg);  in read_fifo()
199 	u32		csr = __raw_readl(creg);  in write_fifo()  local
216 	if (unlikely(csr & (AT91_UDP_TXCOMP | AT91_UDP_TXPKTRDY))) {  in write_fifo()
217 		if (csr & AT91_UDP_TXCOMP) {  in write_fifo()
218 			csr |= CLR_FX;  in write_fifo()
219 			csr &= ~(SET_FX | AT91_UDP_TXCOMP);  in write_fifo()
220 			__raw_writel(csr, creg);  in write_fifo()
221 			csr = __raw_readl(creg);  in write_fifo()
223 		if (csr & AT91_UDP_TXPKTRDY)  in write_fifo()
252 	csr &= ~SET_FX;  in write_fifo()
253 	csr |= CLR_FX | AT91_UDP_TXPKTRDY;  in write_fifo()
254 	__raw_writel(csr, creg);  in write_fifo()
547 	u32		csr;  in at91_ep_set_halt()  local
557 	csr = __raw_readl(creg);  in at91_ep_set_halt()
564 	if (ep->is_in && (!list_empty(&ep->queue) || (csr >> 16) != 0))  in at91_ep_set_halt()
567 		csr |= CLR_FX;  in at91_ep_set_halt()
568 		csr &= ~SET_FX;  in at91_ep_set_halt()
570 			csr |= AT91_UDP_FORCESTALL;  in at91_ep_set_halt()
575 			csr &= ~AT91_UDP_FORCESTALL;  in at91_ep_set_halt()
577 		__raw_writel(csr, creg);  in at91_ep_set_halt()
810 	u32			csr = __raw_readl(creg);  in handle_ep()  local
819 		if (csr & (AT91_UDP_STALLSENT | AT91_UDP_TXCOMP)) {  in handle_ep()
820 			csr |= CLR_FX;  in handle_ep()
821 			csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_TXCOMP);  in handle_ep()
822 			__raw_writel(csr, creg);  in handle_ep()
828 		if (csr & AT91_UDP_STALLSENT) {  in handle_ep()
832 			csr |= CLR_FX;  in handle_ep()
833 			csr &= ~(SET_FX | AT91_UDP_STALLSENT);  in handle_ep()
834 			__raw_writel(csr, creg);  in handle_ep()
835 			csr = __raw_readl(creg);  in handle_ep()
837 		if (req && (csr & RX_DATA_READY))  in handle_ep()
848 static void handle_setup(struct at91_udc *udc, struct at91_ep *ep, u32 csr)  in handle_setup()  argument
858 	rxcount = (csr & AT91_UDP_RXBYTECNT) >> 16;  in handle_setup()
863 			csr |= AT91_UDP_DIR;  in handle_setup()
866 			csr &= ~AT91_UDP_DIR;  in handle_setup()
871 		ERR("SETUP len %d, csr %08x\n", rxcount, csr);  in handle_setup()
874 	csr |= CLR_FX;  in handle_setup()
875 	csr &= ~(SET_FX | AT91_UDP_RXSETUP);  in handle_setup()
876 	__raw_writel(csr, creg);  in handle_setup()
896 	csr = __raw_readl(creg);  in handle_setup()
897 	csr |= CLR_FX;  in handle_setup()
898 	csr &= ~SET_FX;  in handle_setup()
903 		__raw_writel(csr | AT91_UDP_TXPKTRDY, creg);  in handle_setup()
1059 		csr |= AT91_UDP_FORCESTALL;  in handle_setup()
1060 		__raw_writel(csr, creg);  in handle_setup()
1069 	csr |= AT91_UDP_TXPKTRDY;  in handle_setup()
1070 	__raw_writel(csr, creg);  in handle_setup()
1078 	u32			csr = __raw_readl(creg);  in handle_ep0()  local
1081 	if (unlikely(csr & AT91_UDP_STALLSENT)) {  in handle_ep0()
1084 		csr |= CLR_FX;  in handle_ep0()
1085 		csr &= ~(SET_FX | AT91_UDP_STALLSENT | AT91_UDP_FORCESTALL);  in handle_ep0()
1086 		__raw_writel(csr, creg);  in handle_ep0()
1088 		csr = __raw_readl(creg);  in handle_ep0()
1090 	if (csr & AT91_UDP_RXSETUP) {  in handle_ep0()
1093 		handle_setup(udc, ep0, csr);  in handle_ep0()
1103 	if (csr & AT91_UDP_TXCOMP) {  in handle_ep0()
1104 		csr |= CLR_FX;  in handle_ep0()
1105 		csr &= ~(SET_FX | AT91_UDP_TXCOMP);  in handle_ep0()
1122 			__raw_writel(csr, creg);  in handle_ep0()
1146 	else if (csr & AT91_UDP_RX_DATA_BK0) {  in handle_ep0()
1147 		csr |= CLR_FX;  in handle_ep0()
1148 		csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0);  in handle_ep0()
1156 					csr = __raw_readl(creg);  in handle_ep0()
1157 					csr &= ~SET_FX;  in handle_ep0()
1158 					csr |= CLR_FX | AT91_UDP_TXPKTRDY;  in handle_ep0()
1159 					__raw_writel(csr, creg);  in handle_ep0()
1181 				__raw_writel(csr | AT91_UDP_FORCESTALL, creg);  in handle_ep0()
1188 			__raw_writel(csr, creg);  in handle_ep0()