Lines Matching refs:AST_VHUB_EP0_CTRL
46 #define AST_VHUB_EP0_CTRL 0x30 macro
187 writel(EP0_TX_LEN(len), reg + AST_VHUB_EP0_CTRL); in ast_udc_ep0_data_tx()
189 reg + AST_VHUB_EP0_CTRL); in ast_udc_ep0_data_tx()
194 writel(EP0_TX_BUFF_RDY, reg + AST_VHUB_EP0_CTRL); in ast_udc_ep0_data_tx()
226 writel(readl(reg + AST_VHUB_EP0_CTRL) | EP0_STALL, in aspeed_udc_getstatus()
227 reg + AST_VHUB_EP0_CTRL); in aspeed_udc_getstatus()
281 writel(EP0_TX_BUFF_RDY, base + AST_VHUB_EP0_CTRL); in aspeed_udc_setup_handle()
286 writel(EP0_TX_BUFF_RDY, base + AST_VHUB_EP0_CTRL); in aspeed_udc_setup_handle()
335 reg = udc->udc_base + AST_VHUB_EP0_CTRL; in aspeed_udc_ep0_queue()
356 writel(EP0_RX_BUFF_RDY, udc->udc_base + AST_VHUB_EP0_CTRL); in aspeed_udc_ep0_rx()
364 writel(EP0_TX_BUFF_RDY, udc->udc_base + AST_VHUB_EP0_CTRL); in aspeed_udc_ep0_tx()
406 rx_len = EP0_GET_RX_LEN(readl(udc->udc_base + AST_VHUB_EP0_CTRL)); in aspeed_udc_ep0_out()
771 reg = udc->udc_base + AST_VHUB_EP0_CTRL; in aspeed_udc_ep_set_halt()
1155 writel(0, base + AST_VHUB_EP0_CTRL); in udc_init()