Lines Matching +full:tx +full:- +full:freq
1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch-tegra/clk_rst.h>
79 u32 rsvd[56]; /* 028-107 reserved */
81 u32 rsvd2[31]; /* 10c-187 reserved */
88 unsigned int freq; member
97 struct tegra_spi_platdata *plat = bus->platdata; in tegra210_qspi_ofdata_to_platdata()
98 const void *blob = gd->fdt_blob; in tegra210_qspi_ofdata_to_platdata()
101 plat->base = devfdt_get_addr(bus); in tegra210_qspi_ofdata_to_platdata()
102 plat->periph_id = clock_decode_periph_id(bus); in tegra210_qspi_ofdata_to_platdata()
104 if (plat->periph_id == PERIPH_ID_NONE) { in tegra210_qspi_ofdata_to_platdata()
106 plat->periph_id); in tegra210_qspi_ofdata_to_platdata()
107 return -FDT_ERR_NOTFOUND; in tegra210_qspi_ofdata_to_platdata()
111 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", in tegra210_qspi_ofdata_to_platdata()
113 plat->deactivate_delay_us = fdtdec_get_int(blob, node, in tegra210_qspi_ofdata_to_platdata()
114 "spi-deactivate-delay", 0); in tegra210_qspi_ofdata_to_platdata()
115 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", in tegra210_qspi_ofdata_to_platdata()
116 __func__, plat->base, plat->periph_id, plat->frequency, in tegra210_qspi_ofdata_to_platdata()
117 plat->deactivate_delay_us); in tegra210_qspi_ofdata_to_platdata()
127 priv->regs = (struct qspi_regs *)plat->base; in tegra210_qspi_probe()
129 priv->last_transaction_us = timer_get_us(); in tegra210_qspi_probe()
130 priv->freq = plat->frequency; in tegra210_qspi_probe()
131 priv->periph_id = plat->periph_id; in tegra210_qspi_probe()
134 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); in tegra210_qspi_probe()
142 struct qspi_regs *regs = priv->regs; in tegra210_qspi_claim_bus()
145 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq); in tegra210_qspi_claim_bus()
147 debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); in tegra210_qspi_claim_bus()
150 setbits_le32(®s->command1, QSPI_CMD1_M_S | QSPI_CMD1_CS_SW_HW | in tegra210_qspi_claim_bus()
151 (priv->mode << QSPI_CMD1_MODE_SHIFT)); in tegra210_qspi_claim_bus()
152 debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); in tegra210_qspi_claim_bus()
165 struct udevice *bus = dev->parent; in spi_cs_activate()
170 if (pdata->deactivate_delay_us && in spi_cs_activate()
171 priv->last_transaction_us) { in spi_cs_activate()
173 delay_us = timer_get_us() - priv->last_transaction_us; in spi_cs_activate()
174 if (delay_us < pdata->deactivate_delay_us) in spi_cs_activate()
175 udelay(pdata->deactivate_delay_us - delay_us); in spi_cs_activate()
178 clrbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); in spi_cs_activate()
189 struct udevice *bus = dev->parent; in spi_cs_deactivate()
193 setbits_le32(&priv->regs->command1, QSPI_CMD1_CS_SW_VAL); in spi_cs_deactivate()
196 if (pdata->deactivate_delay_us) in spi_cs_deactivate()
197 priv->last_transaction_us = timer_get_us(); in spi_cs_deactivate()
199 debug("Deactivate CS, bus '%s'\n", bus->name); in spi_cs_deactivate()
206 struct udevice *bus = dev->parent; in tegra210_qspi_xfer()
208 struct qspi_regs *regs = priv->regs; in tegra210_qspi_xfer()
215 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); in tegra210_qspi_xfer()
217 return -1; in tegra210_qspi_xfer()
223 reg = readl(®s->fifo_status); in tegra210_qspi_xfer()
224 writel(reg, ®s->fifo_status); in tegra210_qspi_xfer()
226 /* flush RX/TX FIFOs */ in tegra210_qspi_xfer()
227 setbits_le32(®s->fifo_status, in tegra210_qspi_xfer()
232 while ((tm && readl(®s->fifo_status) & in tegra210_qspi_xfer()
235 tm--; in tegra210_qspi_xfer()
242 return -1; in tegra210_qspi_xfer()
247 * 1. don't set LSBY_FE, so no need to swap bytes from/to TX/RX FIFOs; in tegra210_qspi_xfer()
251 * [TODO] I (Yen Lin) have problems when both RX/TX EN bits are set in tegra210_qspi_xfer()
254 clrsetbits_le32(®s->command1, in tegra210_qspi_xfer()
260 writel(0, ®s->dma_blk); in tegra210_qspi_xfer()
265 /* handle data in 32-bit chunks */ in tegra210_qspi_xfer()
275 num_bytes -= bytes; in tegra210_qspi_xfer()
276 writel(tmpdout, ®s->tx_fifo); in tegra210_qspi_xfer()
277 setbits_le32(®s->command1, QSPI_CMD1_TX_EN); in tegra210_qspi_xfer()
281 setbits_le32(®s->command1, QSPI_CMD1_RX_EN); in tegra210_qspi_xfer()
284 setbits_le32(®s->xfer_status, QSPI_XFER_STS_RDY); in tegra210_qspi_xfer()
286 clrsetbits_le32(®s->command1, in tegra210_qspi_xfer()
288 (bytes * 8 - 1) << QSPI_CMD1_BITLEN_SHIFT); in tegra210_qspi_xfer()
292 * "For successful operation at various freq combinations, in tegra210_qspi_xfer()
293 * a minimum of 4-5 spi_clk cycle delay might be required in tegra210_qspi_xfer()
300 setbits_le32(®s->command1, QSPI_CMD1_GO); in tegra210_qspi_xfer()
310 xfer_status = readl(®s->xfer_status); in tegra210_qspi_xfer()
314 fifo_status = readl(®s->fifo_status); in tegra210_qspi_xfer()
318 debug("tx FIFO overflow "); in tegra210_qspi_xfer()
320 debug("tx FIFO underrun "); in tegra210_qspi_xfer()
326 debug("tx FIFO full "); in tegra210_qspi_xfer()
328 debug("tx FIFO empty "); in tegra210_qspi_xfer()
338 tmpdin = readl(®s->rx_fifo); in tegra210_qspi_xfer()
342 num_bytes -= bytes; in tegra210_qspi_xfer()
352 writel(readl(®s->fifo_status), ®s->fifo_status); in tegra210_qspi_xfer()
359 __func__, tmpdin, readl(®s->fifo_status)); in tegra210_qspi_xfer()
364 return -1; in tegra210_qspi_xfer()
372 struct tegra_spi_platdata *plat = bus->platdata; in tegra210_qspi_set_speed()
375 if (speed > plat->frequency) in tegra210_qspi_set_speed()
376 speed = plat->frequency; in tegra210_qspi_set_speed()
377 priv->freq = speed; in tegra210_qspi_set_speed()
378 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); in tegra210_qspi_set_speed()
387 priv->mode = mode; in tegra210_qspi_set_mode()
388 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); in tegra210_qspi_set_mode()
405 { .compatible = "nvidia,tegra210-qspi" },
410 .name = "tegra210-qspi",