Lines Matching +full:tx +full:- +full:freq
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2010-2013 NVIDIA Corporation
12 #include <asm/arch-tegra/clk_rst.h>
80 u32 rsvd[56]; /* 028-107 reserved */
82 u32 rsvd2[31]; /* 10c-187 reserved */
89 unsigned int freq; member
98 struct tegra_spi_platdata *plat = bus->platdata; in tegra114_spi_ofdata_to_platdata()
100 plat->base = dev_read_addr(bus); in tegra114_spi_ofdata_to_platdata()
101 plat->periph_id = clock_decode_periph_id(bus); in tegra114_spi_ofdata_to_platdata()
103 if (plat->periph_id == PERIPH_ID_NONE) { in tegra114_spi_ofdata_to_platdata()
105 plat->periph_id); in tegra114_spi_ofdata_to_platdata()
106 return -FDT_ERR_NOTFOUND; in tegra114_spi_ofdata_to_platdata()
110 plat->frequency = dev_read_u32_default(bus, "spi-max-frequency", in tegra114_spi_ofdata_to_platdata()
112 plat->deactivate_delay_us = dev_read_u32_default(bus, in tegra114_spi_ofdata_to_platdata()
113 "spi-deactivate-delay", 0); in tegra114_spi_ofdata_to_platdata()
114 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n", in tegra114_spi_ofdata_to_platdata()
115 __func__, plat->base, plat->periph_id, plat->frequency, in tegra114_spi_ofdata_to_platdata()
116 plat->deactivate_delay_us); in tegra114_spi_ofdata_to_platdata()
128 priv->regs = (struct spi_regs *)plat->base; in tegra114_spi_probe()
129 regs = priv->regs; in tegra114_spi_probe()
131 priv->last_transaction_us = timer_get_us(); in tegra114_spi_probe()
132 priv->freq = plat->frequency; in tegra114_spi_probe()
133 priv->periph_id = plat->periph_id; in tegra114_spi_probe()
139 rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, in tegra114_spi_probe()
140 priv->freq); in tegra114_spi_probe()
141 if (rate > priv->freq + 100000) { in tegra114_spi_probe()
142 rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC, in tegra114_spi_probe()
143 priv->freq); in tegra114_spi_probe()
144 if (rate != priv->freq) { in tegra114_spi_probe()
146 bus->name, priv->freq, rate); in tegra114_spi_probe()
149 udelay(plat->deactivate_delay_us); in tegra114_spi_probe()
152 setbits_le32(®s->fifo_status, in tegra114_spi_probe()
162 debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status)); in tegra114_spi_probe()
164 setbits_le32(&priv->regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW | in tegra114_spi_probe()
165 (priv->mode << SPI_CMD1_MODE_SHIFT) | SPI_CMD1_CS_SW_VAL); in tegra114_spi_probe()
166 debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1)); in tegra114_spi_probe()
179 struct udevice *bus = dev->parent; in spi_cs_activate()
184 if (pdata->deactivate_delay_us && in spi_cs_activate()
185 priv->last_transaction_us) { in spi_cs_activate()
187 delay_us = timer_get_us() - priv->last_transaction_us; in spi_cs_activate()
188 if (delay_us < pdata->deactivate_delay_us) in spi_cs_activate()
189 udelay(pdata->deactivate_delay_us - delay_us); in spi_cs_activate()
192 clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL); in spi_cs_activate()
203 struct udevice *bus = dev->parent; in spi_cs_deactivate()
207 setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL); in spi_cs_deactivate()
210 if (pdata->deactivate_delay_us) in spi_cs_deactivate()
211 priv->last_transaction_us = timer_get_us(); in spi_cs_deactivate()
213 debug("Deactivate CS, bus '%s'\n", bus->name); in spi_cs_deactivate()
220 struct udevice *bus = dev->parent; in tegra114_spi_xfer()
222 struct spi_regs *regs = priv->regs; in tegra114_spi_xfer()
230 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); in tegra114_spi_xfer()
232 return -1; in tegra114_spi_xfer()
241 reg = readl(®s->fifo_status); in tegra114_spi_xfer()
242 writel(reg, ®s->fifo_status); in tegra114_spi_xfer()
244 clrsetbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL, in tegra114_spi_xfer()
249 writel(0, ®s->dma_blk); in tegra114_spi_xfer()
251 /* handle data in 32-bit chunks */ in tegra114_spi_xfer()
265 num_bytes -= bytes; in tegra114_spi_xfer()
268 setbits_le32(®s->xfer_status, SPI_XFER_STS_RDY); in tegra114_spi_xfer()
270 clrsetbits_le32(®s->command1, in tegra114_spi_xfer()
272 (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT); in tegra114_spi_xfer()
273 writel(tmpdout, ®s->tx_fifo); in tegra114_spi_xfer()
274 setbits_le32(®s->command1, SPI_CMD1_GO); in tegra114_spi_xfer()
283 xfer_status = readl(®s->xfer_status); in tegra114_spi_xfer()
287 fifo_status = readl(®s->fifo_status); in tegra114_spi_xfer()
291 debug("tx FIFO overflow "); in tegra114_spi_xfer()
293 debug("tx FIFO underrun "); in tegra114_spi_xfer()
299 debug("tx FIFO full "); in tegra114_spi_xfer()
301 debug("tx FIFO empty "); in tegra114_spi_xfer()
311 tmpdin = readl(®s->rx_fifo); in tegra114_spi_xfer()
315 for (i = bytes - 1; i >= 0; --i) { in tegra114_spi_xfer()
322 /* We can exit when we've had both RX and TX */ in tegra114_spi_xfer()
331 writel(readl(®s->fifo_status), ®s->fifo_status); in tegra114_spi_xfer()
338 __func__, tmpdin, readl(®s->fifo_status)); in tegra114_spi_xfer()
343 return -1; in tegra114_spi_xfer()
351 struct tegra_spi_platdata *plat = bus->platdata; in tegra114_spi_set_speed()
354 if (speed > plat->frequency) in tegra114_spi_set_speed()
355 speed = plat->frequency; in tegra114_spi_set_speed()
356 priv->freq = speed; in tegra114_spi_set_speed()
357 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq); in tegra114_spi_set_speed()
366 priv->mode = mode; in tegra114_spi_set_mode()
367 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode); in tegra114_spi_set_mode()
383 { .compatible = "nvidia,tegra114-spi" },