Lines Matching +full:dout +full:- +full:default
1 // SPDX-License-Identifier: GPL-2.0+
155 /* default SCK frequency, unit: HZ */
182 clrbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN); in _stm32_qspi_disable()
187 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN); in _stm32_qspi_enable()
192 while (readl(&priv->regs->sr) & STM32_QSPI_SR_BUSY) in _stm32_qspi_wait_for_not_busy()
198 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_TCF)) in _stm32_qspi_wait_for_complete()
204 while (!(readl(&priv->regs->sr) & STM32_QSPI_SR_FTF)) in _stm32_qspi_wait_for_ftf()
210 u32 fsize = fls(size) - 1; in _stm32_qspi_set_flash_size()
212 clrsetbits_le32(&priv->regs->dcr, in _stm32_qspi_set_flash_size()
219 clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL, in _stm32_qspi_set_cs()
227 u32 mode = priv->mode; in _stm32_qspi_gen_ccr()
228 u32 cmd = (priv->command & STM32_QSPI_CCR_INSTRUCTION_MASK); in _stm32_qspi_gen_ccr()
234 if ((priv->command & CMD_HAS_ADR) && (priv->command & CMD_HAS_DATA)) { in _stm32_qspi_gen_ccr()
249 if (priv->command & CMD_HAS_DATA) in _stm32_qspi_gen_ccr()
252 if (priv->command & CMD_HAS_DUMMY) in _stm32_qspi_gen_ccr()
253 ccr_reg |= ((priv->dummycycles & STM32_QSPI_CCR_DCYC_MASK) in _stm32_qspi_gen_ccr()
256 if (priv->command & CMD_HAS_ADR) { in _stm32_qspi_gen_ccr()
274 priv->command = flash->read_opcode | CMD_HAS_ADR | CMD_HAS_DATA in _stm32_qspi_enable_mmap()
276 priv->dummycycles = flash->read_dummy; in _stm32_qspi_enable_mmap()
282 writel(ccr_reg, &priv->regs->ccr); in _stm32_qspi_enable_mmap()
284 priv->dummycycles = 0; in _stm32_qspi_enable_mmap()
289 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_ABORT); in _stm32_qspi_disable_mmap()
295 writel(length - 1, &priv->regs->dlr); in _stm32_qspi_set_xfer_length()
300 writel(cr_reg, &priv->regs->ccr); in _stm32_qspi_start_xfer()
302 if (priv->command & CMD_HAS_ADR) in _stm32_qspi_start_xfer()
303 writel(priv->address, &priv->regs->ar); in _stm32_qspi_start_xfer()
308 const u8 *dout, u8 *din, unsigned long flags) in _stm32_qspi_xfer() argument
323 return -1; in _stm32_qspi_xfer()
327 return -1; in _stm32_qspi_xfer()
330 if (dout && din) { in _stm32_qspi_xfer()
332 return -1; in _stm32_qspi_xfer()
335 if (!dout && (flags & SPI_XFER_BEGIN)) { in _stm32_qspi_xfer()
337 return -1; in _stm32_qspi_xfer()
340 if (dout) { in _stm32_qspi_xfer()
343 priv->command = dout[0] | CMD_HAS_DATA; in _stm32_qspi_xfer()
346 priv->address = (dout[1] << 16) | in _stm32_qspi_xfer()
347 (dout[2] << 8) | dout[3]; in _stm32_qspi_xfer()
348 priv->command |= CMD_HAS_ADR; in _stm32_qspi_xfer()
353 priv->dummycycles = (words - 4) * 8; in _stm32_qspi_xfer()
354 priv->command |= CMD_HAS_DUMMY; in _stm32_qspi_xfer()
359 priv->command &= ~(CMD_HAS_DATA); in _stm32_qspi_xfer()
369 if (priv->command & CMD_HAS_DATA) in _stm32_qspi_xfer()
375 __func__, priv->regs->ccr, priv->regs->ar); in _stm32_qspi_xfer()
377 if (priv->command & CMD_HAS_DATA) { in _stm32_qspi_xfer()
384 writeb(dout[i], &priv->regs->dr); in _stm32_qspi_xfer()
385 debug("%02x ", dout[i]); in _stm32_qspi_xfer()
405 priv->regs->ccr, priv->regs->ar, priv->regs->dlr); in _stm32_qspi_xfer()
411 din[i] = readb(&priv->regs->dr); in _stm32_qspi_xfer()
424 struct stm32_qspi_platdata *plat = bus->platdata; in stm32_qspi_ofdata_to_platdata()
430 return -ENOMEM; in stm32_qspi_ofdata_to_platdata()
435 return -ENOMEM; in stm32_qspi_ofdata_to_platdata()
438 plat->max_hz = dev_read_u32_default(bus, "spi-max-frequency", in stm32_qspi_ofdata_to_platdata()
441 plat->base = res_regs.start; in stm32_qspi_ofdata_to_platdata()
442 plat->memory_map = res_mem.start; in stm32_qspi_ofdata_to_platdata()
444 debug("%s: regs=<0x%x> mapped=<0x%x>, max-frequency=%d\n", in stm32_qspi_ofdata_to_platdata()
446 plat->base, in stm32_qspi_ofdata_to_platdata()
447 plat->memory_map, in stm32_qspi_ofdata_to_platdata()
448 plat->max_hz in stm32_qspi_ofdata_to_platdata()
463 dm_spi_bus = bus->uclass_priv; in stm32_qspi_probe()
465 dm_spi_bus->max_hz = plat->max_hz; in stm32_qspi_probe()
467 priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base; in stm32_qspi_probe()
469 priv->max_hz = plat->max_hz; in stm32_qspi_probe()
482 priv->clock_rate = clk_get_rate(&clk); in stm32_qspi_probe()
483 if (priv->clock_rate < 0) { in stm32_qspi_probe()
485 return priv->clock_rate; in stm32_qspi_probe()
490 if (ret != -ENOENT) { in stm32_qspi_probe()
502 setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT); in stm32_qspi_probe()
519 bus = dev->parent; in stm32_qspi_claim_bus()
524 if (slave_plat->cs >= STM32_MAX_NORCHIP) in stm32_qspi_claim_bus()
525 return -ENODEV; in stm32_qspi_claim_bus()
527 _stm32_qspi_set_cs(priv, slave_plat->cs); in stm32_qspi_claim_bus()
529 _stm32_qspi_set_flash_size(priv, flash->size); in stm32_qspi_claim_bus()
541 bus = dev->parent; in stm32_qspi_release_bus()
550 const void *dout, void *din, unsigned long flags) in stm32_qspi_xfer() argument
556 bus = dev->parent; in stm32_qspi_xfer()
560 return _stm32_qspi_xfer(priv, flash, bitlen, (const u8 *)dout, in stm32_qspi_xfer()
566 struct stm32_qspi_platdata *plat = bus->platdata; in stm32_qspi_set_speed()
568 u32 qspi_clk = priv->clock_rate; in stm32_qspi_set_speed()
572 if (speed > plat->max_hz) in stm32_qspi_set_speed()
573 speed = plat->max_hz; in stm32_qspi_set_speed()
576 prescaler = DIV_ROUND_UP(qspi_clk, speed) - 1; in stm32_qspi_set_speed()
584 csht = (csht - 1) & STM32_QSPI_DCR_CSHT_MASK; in stm32_qspi_set_speed()
588 clrsetbits_le32(&priv->regs->cr, in stm32_qspi_set_speed()
593 clrsetbits_le32(&priv->regs->dcr, in stm32_qspi_set_speed()
597 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, in stm32_qspi_set_speed()
610 setbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE); in stm32_qspi_set_mode()
612 clrbits_le32(&priv->regs->dcr, STM32_QSPI_DCR_CKMODE); in stm32_qspi_set_mode()
614 return -ENODEV; in stm32_qspi_set_mode()
617 return -ENODEV; in stm32_qspi_set_mode()
620 priv->mode |= SPI_RX_QUAD; in stm32_qspi_set_mode()
622 priv->mode |= SPI_RX_DUAL; in stm32_qspi_set_mode()
624 priv->mode &= ~(SPI_RX_QUAD | SPI_RX_DUAL); in stm32_qspi_set_mode()
627 priv->mode |= SPI_TX_QUAD; in stm32_qspi_set_mode()
629 priv->mode |= SPI_TX_DUAL; in stm32_qspi_set_mode()
631 priv->mode &= ~(SPI_TX_QUAD | SPI_TX_DUAL); in stm32_qspi_set_mode()
633 debug("%s: regs=%p, mode=%d rx: ", __func__, priv->regs, mode); in stm32_qspi_set_mode()
661 { .compatible = "st,stm32-qspi" },
662 { .compatible = "st,stm32f469-qspi" },