Lines Matching +full:clk +full:- +full:out +full:- +full:frequency
1 // SPDX-License-Identifier: GPL-2.0+
7 * (C) Copyright 2008-2013 Rockchip Electronics
12 #include <clk.h>
14 #include <dt-structs.h>
31 s32 frequency; /* Default clock frequency, -1 for none */ member
39 struct clk clk; member
55 debug("ctrl0: \t\t0x%08x\n", readl(®s->ctrlr0)); in rkspi_dump_regs()
56 debug("ctrl1: \t\t0x%08x\n", readl(®s->ctrlr1)); in rkspi_dump_regs()
57 debug("ssienr: \t\t0x%08x\n", readl(®s->enr)); in rkspi_dump_regs()
58 debug("ser: \t\t0x%08x\n", readl(®s->ser)); in rkspi_dump_regs()
59 debug("baudr: \t\t0x%08x\n", readl(®s->baudr)); in rkspi_dump_regs()
60 debug("txftlr: \t\t0x%08x\n", readl(®s->txftlr)); in rkspi_dump_regs()
61 debug("rxftlr: \t\t0x%08x\n", readl(®s->rxftlr)); in rkspi_dump_regs()
62 debug("txflr: \t\t0x%08x\n", readl(®s->txflr)); in rkspi_dump_regs()
63 debug("rxflr: \t\t0x%08x\n", readl(®s->rxflr)); in rkspi_dump_regs()
64 debug("sr: \t\t0x%08x\n", readl(®s->sr)); in rkspi_dump_regs()
65 debug("imr: \t\t0x%08x\n", readl(®s->imr)); in rkspi_dump_regs()
66 debug("isr: \t\t0x%08x\n", readl(®s->isr)); in rkspi_dump_regs()
67 debug("dmacr: \t\t0x%08x\n", readl(®s->dmacr)); in rkspi_dump_regs()
68 debug("dmatdlr: \t0x%08x\n", readl(®s->dmatdlr)); in rkspi_dump_regs()
69 debug("dmardlr: \t0x%08x\n", readl(®s->dmardlr)); in rkspi_dump_regs()
74 writel(enable ? 1 : 0, ®s->enr); in rkspi_enable_chip()
83 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); in rkspi_set_clk()
95 __func__, speed, priv->input_rate / clk_div); in rkspi_set_clk()
103 clrsetbits_le32(&priv->regs->baudr, 0xffff, clk_div); in rkspi_set_clk()
104 priv->last_speed_hz = speed; in rkspi_set_clk()
112 while (readl(®s->sr) & SR_BUSY) { in rkspi_wait_till_not_busy()
115 return -ETIMEDOUT; in rkspi_wait_till_not_busy()
124 struct udevice *bus = dev->parent; in spi_cs_activate()
125 struct rockchip_spi_platdata *plat = bus->platdata; in spi_cs_activate()
127 struct rockchip_spi *regs = priv->regs; in spi_cs_activate()
130 if (plat->deactivate_delay_us && priv->last_transaction_us) { in spi_cs_activate()
132 delay_us = timer_get_us() - priv->last_transaction_us; in spi_cs_activate()
133 if (delay_us < plat->deactivate_delay_us) in spi_cs_activate()
134 udelay(plat->deactivate_delay_us - delay_us); in spi_cs_activate()
138 writel(1 << cs, ®s->ser); in spi_cs_activate()
139 if (plat->activate_delay_us) in spi_cs_activate()
140 udelay(plat->activate_delay_us); in spi_cs_activate()
145 struct udevice *bus = dev->parent; in spi_cs_deactivate()
146 struct rockchip_spi_platdata *plat = bus->platdata; in spi_cs_deactivate()
148 struct rockchip_spi *regs = priv->regs; in spi_cs_deactivate()
151 writel(0, ®s->ser); in spi_cs_deactivate()
154 if (plat->deactivate_delay_us) in spi_cs_deactivate()
155 priv->last_transaction_us = timer_get_us(); in spi_cs_deactivate()
161 struct rockchip_spi_platdata *plat = dev->platdata; in conv_of_platdata()
162 struct dtd_rockchip_rk3288_spi *dtplat = &plat->of_plat; in conv_of_platdata()
166 plat->base = dtplat->reg[0]; in conv_of_platdata()
167 plat->frequency = 20000000; in conv_of_platdata()
168 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); in conv_of_platdata()
171 dev->req_seq = 0; in conv_of_platdata()
184 plat->base = dev_read_addr(bus); in rockchip_spi_ofdata_to_platdata()
186 ret = clk_get_by_index(bus, 0, &priv->clk); in rockchip_spi_ofdata_to_platdata()
189 bus->name, ret); in rockchip_spi_ofdata_to_platdata()
193 plat->frequency = in rockchip_spi_ofdata_to_platdata()
194 dev_read_u32_default(bus, "spi-max-frequency", 50000000); in rockchip_spi_ofdata_to_platdata()
195 plat->deactivate_delay_us = in rockchip_spi_ofdata_to_platdata()
196 dev_read_u32_default(bus, "spi-deactivate-delay", 0); in rockchip_spi_ofdata_to_platdata()
197 plat->activate_delay_us = in rockchip_spi_ofdata_to_platdata()
198 dev_read_u32_default(bus, "spi-activate-delay", 0); in rockchip_spi_ofdata_to_platdata()
200 debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", in rockchip_spi_ofdata_to_platdata()
201 __func__, (uint)plat->base, plat->frequency, in rockchip_spi_ofdata_to_platdata()
202 plat->deactivate_delay_us); in rockchip_spi_ofdata_to_platdata()
213 * clk_set_rate(...) implementation in our clock-driver will in rockchip_spi_calc_modclk()
223 * the maximum frequency and can be generated from the assumed in rockchip_spi_calc_modclk()
227 * are generated by dividing by an even 16-bit integer from in rockchip_spi_calc_modclk()
228 * this frequency), we try to have an input frequency of at in rockchip_spi_calc_modclk()
248 priv->regs = (struct rockchip_spi *)plat->base; in rockchip_spi_probe()
250 priv->last_transaction_us = timer_get_us(); in rockchip_spi_probe()
251 priv->max_freq = plat->frequency; in rockchip_spi_probe()
254 if (priv->max_freq > ROCKCHIP_SPI_MAX_RATE) in rockchip_spi_probe()
255 priv->max_freq = ROCKCHIP_SPI_MAX_RATE; in rockchip_spi_probe()
257 /* Find a module-input clock that fits with the max_freq setting */ in rockchip_spi_probe()
258 ret = clk_set_rate(&priv->clk, in rockchip_spi_probe()
259 rockchip_spi_calc_modclk(priv->max_freq)); in rockchip_spi_probe()
264 priv->input_rate = ret; in rockchip_spi_probe()
265 debug("%s: rate = %u\n", __func__, priv->input_rate); in rockchip_spi_probe()
266 priv->bits_per_word = 8; in rockchip_spi_probe()
267 priv->tmode = TMOD_TR; /* Tx & Rx */ in rockchip_spi_probe()
274 struct udevice *bus = dev->parent; in rockchip_spi_claim_bus()
276 struct rockchip_spi *regs = priv->regs; in rockchip_spi_claim_bus()
283 switch (priv->bits_per_word) { in rockchip_spi_claim_bus()
285 priv->n_bytes = 1; in rockchip_spi_claim_bus()
290 priv->n_bytes = 2; in rockchip_spi_claim_bus()
296 priv->bits_per_word); in rockchip_spi_claim_bus()
297 return -EPROTONOSUPPORT; in rockchip_spi_claim_bus()
300 if (priv->speed_hz != priv->last_speed_hz) in rockchip_spi_claim_bus()
301 rkspi_set_clk(priv, priv->speed_hz); in rockchip_spi_claim_bus()
310 if (priv->mode & SPI_CPOL) in rockchip_spi_claim_bus()
312 if (priv->mode & SPI_CPHA) in rockchip_spi_claim_bus()
337 ctrlr0 |= (priv->tmode & TMOD_MASK) << TMOD_SHIFT; in rockchip_spi_claim_bus()
339 writel(ctrlr0, ®s->ctrlr0); in rockchip_spi_claim_bus()
346 struct udevice *bus = dev->parent; in rockchip_spi_release_bus()
349 rkspi_enable_chip(priv->regs, false); in rockchip_spi_release_bus()
357 struct udevice *bus = dev->parent; in rockchip_spi_xfer()
359 struct rockchip_spi *regs = priv->regs; in rockchip_spi_xfer()
362 const u8 *out = dout; in rockchip_spi_xfer() local
374 spi_cs_activate(dev, slave_plat->cs); in rockchip_spi_xfer()
380 writel(todo - 1, ®s->ctrlr1); in rockchip_spi_xfer()
386 u32 status = readl(®s->sr); in rockchip_spi_xfer()
389 writel(out ? *out++ : 0, regs->txdr); in rockchip_spi_xfer()
390 towrite--; in rockchip_spi_xfer()
393 u32 byte = readl(regs->rxdr); in rockchip_spi_xfer()
397 toread--; in rockchip_spi_xfer()
403 len -= todo; in rockchip_spi_xfer()
408 spi_cs_deactivate(dev, slave_plat->cs); in rockchip_spi_xfer()
419 /* Clamp to the maximum frequency specified in the DTS */ in rockchip_spi_set_speed()
420 if (speed > priv->max_freq) in rockchip_spi_set_speed()
421 speed = priv->max_freq; in rockchip_spi_set_speed()
423 priv->speed_hz = speed; in rockchip_spi_set_speed()
432 priv->mode = mode; in rockchip_spi_set_mode()
450 { .compatible = "rockchip,rk3288-spi" },
451 { .compatible = "rockchip,rk3368-spi" },
452 { .compatible = "rockchip,rk3399-spi" },