1 // SPDX-License-Identifier: GPL-2.0+
45 /* SSP Control Register 0  - SSP_CR0 */
48 #define SSP_CR0_BIT_MODE(x)	((x) - 1)
54 /* SSP Control Register 1  - SSP_CR1 */
61 /* SSP Status Register - SSP_SR */
81 	if ((readw(ps->base + SSP_PID0) == 0x22) &&  in pl022_is_supported()
82 	    (readw(ps->base + SSP_PID1) == 0x10) &&  in pl022_is_supported()
83 	    ((readw(ps->base + SSP_PID2) & 0xf) == 0x04) &&  in pl022_is_supported()
84 	    (readw(ps->base + SSP_PID3) == 0x00))  in pl022_is_supported()
95 	ps->base = ioremap(plat->addr, plat->size);  in pl022_spi_probe()
96 	ps->freq = plat->freq;  in pl022_spi_probe()
100 		return -ENOTSUPP;  in pl022_spi_probe()
103 	writew(SSP_CR0_BIT_MODE(8), ps->base + SSP_CR0);  in pl022_spi_probe()
104 	writew(DFLT_PRESCALE, ps->base + SSP_CPSR);  in pl022_spi_probe()
112 		while (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE)  in flush()
113 			readw(ps->base + SSP_DR);  in flush()
114 	} while (readw(ps->base + SSP_SR) & SSP_SR_MASK_BSY);  in flush()
119 	struct udevice *bus = dev->parent;  in pl022_spi_claim_bus()
124 	reg = readw(ps->base + SSP_CR1);  in pl022_spi_claim_bus()
126 	writew(reg, ps->base + SSP_CR1);  in pl022_spi_claim_bus()
135 	struct udevice *bus = dev->parent;  in pl022_spi_release_bus()
142 	reg = readw(ps->base + SSP_CR1);  in pl022_spi_release_bus()
144 	writew(reg, ps->base + SSP_CR1);  in pl022_spi_release_bus()
152 	struct udevice *bus = dev->parent;  in pl022_spi_xfer()
164 	 * TODO: The controller can do non-multiple-of-8 bit  in pl022_spi_xfer()
174 		return -1;  in pl022_spi_xfer()
180 		if (readw(ps->base + SSP_SR) & SSP_SR_MASK_TNF) {  in pl022_spi_xfer()
182 			writew(value, ps->base + SSP_DR);  in pl022_spi_xfer()
186 		if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {  in pl022_spi_xfer()
187 			value = readw(ps->base + SSP_DR);  in pl022_spi_xfer()
195 		if (readw(ps->base + SSP_SR) & SSP_SR_MASK_RNE) {  in pl022_spi_xfer()
196 			value = readw(ps->base + SSP_DR);  in pl022_spi_xfer()
211 static int pl022_spi_set_speed(struct udevice *bus, uint speed)  in pl022_spi_set_speed()  argument
216 	u32 min, max, best_freq = 0, tmp;  in pl022_spi_set_speed()  local
217 	u32 rate = ps->freq;  in pl022_spi_set_speed()
220 	max = spi_rate(rate, SSP_CPSR_MIN, SSP_SCR_MIN);  in pl022_spi_set_speed()
223 	if (speed > max || speed < min) {  in pl022_spi_set_speed()
224 		pr_err("Tried to set speed to %dHz but min=%d and max=%d\n",  in pl022_spi_set_speed()
225 		       speed, min, max);  in pl022_spi_set_speed()
226 		return -EINVAL;  in pl022_spi_set_speed()
233 			if (abs(speed - tmp) < abs(speed - best_freq)) {  in pl022_spi_set_speed()
238 				if (tmp == speed) {  in pl022_spi_set_speed()
250 	writew(best_cpsr, ps->base + SSP_CPSR);  in pl022_spi_set_speed()
251 	cr0 = readw(ps->base + SSP_CR0);  in pl022_spi_set_speed()
252 	writew(cr0 | (best_scr << SSP_SCR_SHFT), ps->base + SSP_CR0);  in pl022_spi_set_speed()
262 	reg = readw(ps->base + SSP_CR0);  in pl022_spi_set_mode()
268 	writew(reg, ps->base + SSP_CR0);  in pl022_spi_set_mode()
291 	struct pl022_spi_pdata *plat = bus->platdata;  in pl022_spi_ofdata_to_platdata()
292 	const void *fdt = gd->fdt_blob;  in pl022_spi_ofdata_to_platdata()
297 	plat->addr = fdtdec_get_addr_size(fdt, node, "reg", &plat->size);  in pl022_spi_ofdata_to_platdata()
303 	plat->freq = clk_get_rate(&clkdev);  in pl022_spi_ofdata_to_platdata()
309 	{ .compatible = "arm,pl022-spi" },