138 static u32 qspi_read32(u32 flags, u32 *addr)  in qspi_read32()  function
158 		val = qspi_read32(priv->flags, &priv->regs->sr);  in is_controller_busy()
383 	reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_ahb_invalid()
404 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_ahb_read()
422 	reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_enable_ddr_mode()
427 	reg2 = qspi_read32(priv->flags, &regs->smpr);  in qspi_enable_ddr_mode()
488 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_rdbank()
505 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_rdbank()
511 		reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_rdbank()
513 			data = qspi_read32(priv->flags, &regs->rbdr[0]);  in qspi_op_rdbank()
517 				     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_rdbank()
533 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_rdid()
543 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_rdid()
550 		rbsr_reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_rdid()
552 			data = qspi_read32(priv->flags, &regs->rbdr[i]);  in qspi_op_rdid()
579 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_read()
598 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_read()
606 			data = qspi_read32(priv->flags, &regs->rbdr[i]);  in qspi_op_read()
617 			     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_read()
631 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_write()
643 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_write()
648 		while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_write()
651 		reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_write()
653 			status_reg = qspi_read32(priv->flags, &regs->rbdr[0]);  in qspi_op_write()
657 			     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_write()
695 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_write()
706 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_rdsr()
716 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_rdsr()
722 		reg = qspi_read32(priv->flags, &regs->rbsr);  in qspi_op_rdsr()
724 			data = qspi_read32(priv->flags, &regs->rbdr[0]);  in qspi_op_rdsr()
728 				     qspi_read32(priv->flags, &regs->mcr) |  in qspi_op_rdsr()
743 	mcr_reg = qspi_read32(priv->flags, &regs->mcr);  in qspi_op_erase()
754 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_erase()
764 	while (qspi_read32(priv->flags, &regs->sr) & QSPI_SR_BUSY_MASK)  in qspi_op_erase()
847 	mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);  in qspi_module_disable()
859 	smpr_val = qspi_read32(priv->flags, &priv->regs->smpr);  in qspi_cfg_smpr()
909 	mcr_val = qspi_read32(priv->flags, &priv->regs->mcr);  in fsl_qspi_probe()