Lines Matching +full:pre +full:- +full:scaler
1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2000-2003
6 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
42 /* CTAR register pre-configure value */
51 /* CTAR register pre-configure mask */
61 * struct fsl_dspi_platdata - platform data for Freescale DSPI
76 * struct fsl_dspi_priv - private data for Freescale DSPI
136 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr); in dspi_halt()
143 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val); in dspi_halt()
151 dspi_write32(priv->flags, &priv->regs->mcr, cfg_val); in fsl_dspi_init_mcr()
156 priv->mcr_val = cfg_val; in fsl_dspi_init_mcr()
166 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr); in fsl_dspi_cfg_cs_active_state()
173 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val); in fsl_dspi_cfg_cs_active_state()
183 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]); in fsl_dspi_cfg_ctar_mode()
186 bus_setup |= priv->ctar_val[cs]; in fsl_dspi_cfg_ctar_mode()
196 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup); in fsl_dspi_cfg_ctar_mode()
198 priv->charbit = in fsl_dspi_cfg_ctar_mode()
199 ((dspi_read32(priv->flags, &priv->regs->ctar[0]) & in fsl_dspi_cfg_ctar_mode()
210 mcr_val = dspi_read32(priv->flags, &priv->regs->mcr); in fsl_dspi_clr_fifo()
213 dspi_write32(priv->flags, &priv->regs->mcr, mcr_val); in fsl_dspi_clr_fifo()
222 while (DSPI_SR_TXCTR(dspi_read32(priv->flags, &priv->regs->sr)) >= 4 && in dspi_tx()
223 timeout--) in dspi_tx()
227 dspi_write32(priv->flags, &priv->regs->tfr, (ctrl | data)); in dspi_tx()
237 while (DSPI_SR_RXCTR(dspi_read32(priv->flags, &priv->regs->sr)) == 0 && in dspi_rx()
238 timeout--) in dspi_rx()
243 dspi_read32(priv->flags, &priv->regs->rfr)); in dspi_rx()
258 if (priv->charbit == 16) { in dspi_xfer()
274 int tmp_len = len - 1; in dspi_xfer()
275 while (tmp_len--) { in dspi_xfer()
277 if (priv->charbit == 16) in dspi_xfer()
286 if (priv->charbit == 16) in dspi_xfer()
301 if (priv->charbit == 16) in dspi_xfer()
310 if (priv->charbit == 16) in dspi_xfer()
330 * @br: return Baud Rate Scaler value
337 /* Valid baud rate pre-scaler values */ in fsl_dspi_hz_to_spi_baud()
359 *pbr = ARRAY_SIZE(pbr_tbl) - 1; in fsl_dspi_hz_to_spi_baud()
360 *br = ARRAY_SIZE(brs) - 1; in fsl_dspi_hz_to_spi_baud()
361 return -EINVAL; in fsl_dspi_hz_to_spi_baud()
370 bus_clk = priv->bus_clk; in fsl_dspi_cfg_speed()
375 bus_setup = dspi_read32(priv->flags, &priv->regs->ctar[0]); in fsl_dspi_cfg_speed()
380 speed = priv->speed_hz; in fsl_dspi_cfg_speed()
386 dspi_write32(priv->flags, &priv->regs->ctar[0], bus_setup); in fsl_dspi_cfg_speed()
388 priv->speed_hz = speed; in fsl_dspi_cfg_speed()
414 dspi->priv.flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG; in spi_setup_slave()
417 dspi->priv.regs = (struct dspi *)MMAP_DSPI; in spi_setup_slave()
420 dspi->priv.bus_clk = gd->bus_clk; in spi_setup_slave()
422 dspi->priv.bus_clk = mxc_get_clock(MXC_DSPI_CLK); in spi_setup_slave()
424 dspi->priv.speed_hz = FSL_DSPI_DEFAULT_SCK_FREQ; in spi_setup_slave()
429 fsl_dspi_init_mcr(&dspi->priv, mcr_cfg_val); in spi_setup_slave()
432 dspi->priv.ctar_val[i] = DSPI_CTAR_DEFAULT_VALUE; in spi_setup_slave()
436 dspi->priv.ctar_val[0] = CONFIG_SYS_DSPI_CTAR0; in spi_setup_slave()
440 dspi->priv.ctar_val[1] = CONFIG_SYS_DSPI_CTAR1; in spi_setup_slave()
444 dspi->priv.ctar_val[2] = CONFIG_SYS_DSPI_CTAR2; in spi_setup_slave()
448 dspi->priv.ctar_val[3] = CONFIG_SYS_DSPI_CTAR3; in spi_setup_slave()
452 dspi->priv.ctar_val[4] = CONFIG_SYS_DSPI_CTAR4; in spi_setup_slave()
456 dspi->priv.ctar_val[5] = CONFIG_SYS_DSPI_CTAR5; in spi_setup_slave()
460 dspi->priv.ctar_val[6] = CONFIG_SYS_DSPI_CTAR6; in spi_setup_slave()
464 dspi->priv.ctar_val[7] = CONFIG_SYS_DSPI_CTAR7; in spi_setup_slave()
467 fsl_dspi_cfg_speed(&dspi->priv, max_hz); in spi_setup_slave()
470 fsl_dspi_cfg_ctar_mode(&dspi->priv, cs, mode); in spi_setup_slave()
473 fsl_dspi_cfg_cs_active_state(&dspi->priv, cs, mode); in spi_setup_slave()
475 return &dspi->slave; in spi_setup_slave()
488 cpu_dspi_claim_bus(slave->bus, slave->cs); in spi_claim_bus()
490 fsl_dspi_clr_fifo(&dspi->priv); in spi_claim_bus()
493 sr_val = dspi_read32(dspi->priv.flags, &dspi->priv.regs->sr); in spi_claim_bus()
496 return -EIO; in spi_claim_bus()
506 dspi_halt(&dspi->priv, 1); in spi_release_bus()
507 cpu_dspi_release_bus(slave->bus.slave->cs); in spi_release_bus()
514 return dspi_xfer(&dspi->priv, slave->cs, bitlen, dout, din, flags); in spi_xfer()
520 struct fsl_dspi_priv *priv = dev_get_priv(dev->parent); in fsl_dspi_child_pre_probe()
522 if (slave_plat->cs >= priv->num_chipselect) { in fsl_dspi_child_pre_probe()
524 slave_plat->cs, priv->num_chipselect - 1); in fsl_dspi_child_pre_probe()
525 return -EINVAL; in fsl_dspi_child_pre_probe()
528 priv->ctar_val[slave_plat->cs] = DSPI_CTAR_DEFAULT_VALUE; in fsl_dspi_child_pre_probe()
531 slave_plat->cs, slave_plat->max_hz, slave_plat->mode); in fsl_dspi_child_pre_probe()
543 dm_spi_bus = bus->uclass_priv; in fsl_dspi_probe()
549 priv->regs = (struct dspi *)plat->regs_addr; in fsl_dspi_probe()
550 priv->flags = plat->flags; in fsl_dspi_probe()
552 priv->bus_clk = gd->bus_clk; in fsl_dspi_probe()
554 priv->bus_clk = mxc_get_clock(MXC_DSPI_CLK); in fsl_dspi_probe()
556 priv->num_chipselect = plat->num_chipselect; in fsl_dspi_probe()
557 priv->speed_hz = plat->speed_hz; in fsl_dspi_probe()
559 priv->charbit = 8; in fsl_dspi_probe()
561 dm_spi_bus->max_hz = plat->speed_hz; in fsl_dspi_probe()
568 debug("%s probe done, bus-num %d.\n", bus->name, bus->seq); in fsl_dspi_probe()
577 struct udevice *bus = dev->parent; in fsl_dspi_claim_bus()
584 cpu_dspi_claim_bus(bus->seq, slave_plat->cs); in fsl_dspi_claim_bus()
587 fsl_dspi_cfg_ctar_mode(priv, slave_plat->cs, priv->mode); in fsl_dspi_claim_bus()
590 fsl_dspi_cfg_cs_active_state(priv, slave_plat->cs, in fsl_dspi_claim_bus()
591 priv->mode); in fsl_dspi_claim_bus()
596 sr_val = dspi_read32(priv->flags, &priv->regs->sr); in fsl_dspi_claim_bus()
599 return -EIO; in fsl_dspi_claim_bus()
607 struct udevice *bus = dev->parent; in fsl_dspi_release_bus()
616 cpu_dspi_release_bus(bus->seq, slave_plat->cs); in fsl_dspi_release_bus()
626 debug("%s assigned req_seq %d.\n", bus->name, bus->req_seq); in fsl_dspi_bind()
633 struct fsl_dspi_platdata *plat = bus->platdata; in fsl_dspi_ofdata_to_platdata()
634 const void *blob = gd->fdt_blob; in fsl_dspi_ofdata_to_platdata()
637 if (fdtdec_get_bool(blob, node, "big-endian")) in fsl_dspi_ofdata_to_platdata()
638 plat->flags |= DSPI_FLAG_REGMAP_ENDIAN_BIG; in fsl_dspi_ofdata_to_platdata()
640 plat->num_chipselect = in fsl_dspi_ofdata_to_platdata()
641 fdtdec_get_int(blob, node, "num-cs", FSL_DSPI_MAX_CHIPSELECT); in fsl_dspi_ofdata_to_platdata()
646 return -ENOMEM; in fsl_dspi_ofdata_to_platdata()
648 plat->regs_addr = addr; in fsl_dspi_ofdata_to_platdata()
650 plat->speed_hz = fdtdec_get_int(blob, in fsl_dspi_ofdata_to_platdata()
651 node, "spi-max-frequency", FSL_DSPI_DEFAULT_SCK_FREQ); in fsl_dspi_ofdata_to_platdata()
653 debug("DSPI: regs=%pa, max-frequency=%d, endianess=%s, num-cs=%d\n", in fsl_dspi_ofdata_to_platdata()
654 &plat->regs_addr, plat->speed_hz, in fsl_dspi_ofdata_to_platdata()
655 plat->flags & DSPI_FLAG_REGMAP_ENDIAN_BIG ? "be" : "le", in fsl_dspi_ofdata_to_platdata()
656 plat->num_chipselect); in fsl_dspi_ofdata_to_platdata()
668 bus = dev->parent; in fsl_dspi_xfer()
671 return dspi_xfer(priv, slave_plat->cs, bitlen, dout, din, flags); in fsl_dspi_xfer()
688 * We store some chipselect special configure value in priv->ctar_val, in fsl_dspi_set_mode()
693 priv->mode = mode; in fsl_dspi_set_mode()
707 { .compatible = "fsl,vf610-dspi" },