166 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base)			\  argument
167 	(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>	\
170 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base)			\  argument
171 	(((readl(reg_base + CQSPI_REG_SDRAMLEVEL)) >>	\
187 void cadence_qspi_apb_controller_enable(void *reg_base)  in cadence_qspi_apb_controller_enable()  argument
190 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_controller_enable()
192 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_controller_enable()
195 void cadence_qspi_apb_controller_disable(void *reg_base)  in cadence_qspi_apb_controller_disable()  argument
198 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_controller_disable()
200 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_controller_disable()
204 static unsigned int cadence_qspi_wait_idle(void *reg_base)  in cadence_qspi_wait_idle()  argument
212 		if (CQSPI_REG_IS_IDLE(reg_base))  in cadence_qspi_wait_idle()
230 void cadence_qspi_apb_readdata_capture(void *reg_base,  in cadence_qspi_apb_readdata_capture()  argument
234 	cadence_qspi_apb_controller_disable(reg_base);  in cadence_qspi_apb_readdata_capture()
236 	reg = readl(reg_base + CQSPI_REG_RD_DATA_CAPTURE);  in cadence_qspi_apb_readdata_capture()
249 	writel(reg, reg_base + CQSPI_REG_RD_DATA_CAPTURE);  in cadence_qspi_apb_readdata_capture()
251 	cadence_qspi_apb_controller_enable(reg_base);  in cadence_qspi_apb_readdata_capture()
254 void cadence_qspi_apb_config_baudrate_div(void *reg_base,  in cadence_qspi_apb_config_baudrate_div()  argument
260 	cadence_qspi_apb_controller_disable(reg_base);  in cadence_qspi_apb_config_baudrate_div()
261 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_config_baudrate_div()
279 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_config_baudrate_div()
281 	cadence_qspi_apb_controller_enable(reg_base);  in cadence_qspi_apb_config_baudrate_div()
284 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode)  in cadence_qspi_apb_set_clk_mode()  argument
288 	cadence_qspi_apb_controller_disable(reg_base);  in cadence_qspi_apb_set_clk_mode()
289 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_set_clk_mode()
297 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_set_clk_mode()
299 	cadence_qspi_apb_controller_enable(reg_base);  in cadence_qspi_apb_set_clk_mode()
302 void cadence_qspi_apb_chipselect(void *reg_base,  in cadence_qspi_apb_chipselect()  argument
307 	cadence_qspi_apb_controller_disable(reg_base);  in cadence_qspi_apb_chipselect()
312 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_chipselect()
331 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_chipselect()
333 	cadence_qspi_apb_controller_enable(reg_base);  in cadence_qspi_apb_chipselect()
336 void cadence_qspi_apb_delay(void *reg_base,  in cadence_qspi_apb_delay()  argument
346 	cadence_qspi_apb_controller_disable(reg_base);  in cadence_qspi_apb_delay()
372 	writel(reg, reg_base + CQSPI_REG_DELAY);  in cadence_qspi_apb_delay()
374 	cadence_qspi_apb_controller_enable(reg_base);  in cadence_qspi_apb_delay()
404 static int cadence_qspi_apb_exec_flash_cmd(void *reg_base,  in cadence_qspi_apb_exec_flash_cmd()  argument
410 	writel(reg, reg_base + CQSPI_REG_CMDCTRL);  in cadence_qspi_apb_exec_flash_cmd()
413 	writel(reg, reg_base + CQSPI_REG_CMDCTRL);  in cadence_qspi_apb_exec_flash_cmd()
416 		reg = readl(reg_base + CQSPI_REG_CMDCTRL);  in cadence_qspi_apb_exec_flash_cmd()
428 	if (!cadence_qspi_wait_idle(reg_base))  in cadence_qspi_apb_exec_flash_cmd()
435 int cadence_qspi_apb_command_read(void *reg_base,  in cadence_qspi_apb_command_read()  argument
456 	status = cadence_qspi_apb_exec_flash_cmd(reg_base, reg);  in cadence_qspi_apb_command_read()
460 	reg = readl(reg_base + CQSPI_REG_CMDREADDATALOWER);  in cadence_qspi_apb_command_read()
468 		reg = readl(reg_base + CQSPI_REG_CMDREADDATAUPPER);  in cadence_qspi_apb_command_read()
477 int cadence_qspi_apb_command_write(void *reg_base, unsigned int cmdlen,  in cadence_qspi_apb_command_write()  argument
503 		writel(addr_value, reg_base + CQSPI_REG_CMDADDRESS);  in cadence_qspi_apb_command_write()
514 		writel(wr_data, reg_base +  in cadence_qspi_apb_command_write()
521 			writel(wr_data, reg_base +  in cadence_qspi_apb_command_write()
527 	return cadence_qspi_apb_exec_flash_cmd(reg_base, reg);  in cadence_qspi_apb_command_write()
791 void cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy)  in cadence_qspi_apb_enter_xip()  argument
796 	reg = readl(reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_enter_xip()
800 	writel(reg, reg_base + CQSPI_REG_CONFIG);  in cadence_qspi_apb_enter_xip()
803 	writel(xip_dummy, reg_base + CQSPI_REG_MODE_BIT);  in cadence_qspi_apb_enter_xip()
806 	reg = readl(reg_base + CQSPI_REG_RD_INSTR);  in cadence_qspi_apb_enter_xip()
808 	writel(reg, reg_base + CQSPI_REG_RD_INSTR);  in cadence_qspi_apb_enter_xip()