Lines Matching defs:aspeed_spi_regs
22 struct aspeed_spi_regs { struct
23 u32 conf; /* 0x00 CE Type Setting */
24 u32 ctrl; /* 0x04 Control */
25 u32 intr_ctrl; /* 0x08 Interrupt Control and Status */
26 u32 cmd_ctrl; /* 0x0c Command Control */
27 u32 ce_ctrl[ASPEED_SPI_MAX_CS]; /* 0x10 .. 0x18 CEx Control */
28 u32 _reserved0[5]; /* .. */
29 u32 segment_addr[ASPEED_SPI_MAX_CS];
31 u32 _reserved1[5]; /* .. */
32 u32 soft_rst_cmd_ctrl; /* 0x50 Auto Soft-Reset Command Control */
33 u32 _reserved2[11]; /* .. */
34 u32 dma_ctrl; /* 0x80 DMA Control/Status */
35 u32 dma_flash_addr; /* 0x84 DMA Flash Side Address */
36 u32 dma_dram_addr; /* 0x88 DMA DRAM Side Address */
37 u32 dma_len; /* 0x8c DMA Length Register */
38 u32 dma_checksum; /* 0x90 Checksum Calculation Result */
39 u32 timings; /* 0x94 Read Timing Compensation */
40 u32 _reserved3[1];
42 u32 soft_strap_status; /* 0x9c Software Strap Status */
43 u32 write_cmd_filter_ctrl; /* 0xa0 Write Command Filter Control */
44 u32 write_addr_filter_ctrl; /* 0xa4 Write Address Filter Control */
45 u32 lock_ctrl_reset; /* 0xa8 Lock Control (SRST#) */
46 u32 lock_ctrl_wdt; /* 0xac Lock Control (Watchdog) */
47 u32 write_addr_filter[8]; /* 0xb0 Write Address Filter */
48 u32 _reserved4[12];
49 u32 fully_qualified_cmd[20]; /* 0x100 Fully Qualified Command */
50 u32 addr_qualified_cmd[12]; /* 0x150 Address Qualified Command */