Lines Matching full:14

307 #define RT5677_VOL_L_MUTE			(0x1 << 14)
308 #define RT5677_VOL_L_SFT			14
321 #define RT5677_LOUT1_L_DF			(0x1 << 14)
322 #define RT5677_LOUT1_L_DF_SFT			(14)
353 #define RT5677_MICBIAS1_CTRL_VDD_MASK		(0x1 << 14)
354 #define RT5677_MICBIAS1_CTRL_VDD_SFT		(14)
355 #define RT5677_MICBIAS1_CTRL_VDD_1_8V		(0x0 << 14)
356 #define RT5677_MICBIAS1_CTRL_VDD_3_3V		(0x1 << 14)
462 #define RT5677_STO1_ADC_L_BST_MASK		(0x3 << 14)
463 #define RT5677_STO1_ADC_L_BST_SFT		14
482 #define RT5677_MONO_ADC_L_BST_MASK		(0x3 << 14)
483 #define RT5677_MONO_ADC_L_BST_SFT		14
490 #define RT5677_STO3_ADC_L_BST_MASK		(0x3 << 14)
491 #define RT5677_STO3_ADC_L_BST_SFT		14
518 #define RT5677_M_STO4_ADC_L1			(0x1 << 14)
519 #define RT5677_M_STO4_ADC_L1_SFT		14
534 #define RT5677_M_STO3_ADC_L1			(0x1 << 14)
535 #define RT5677_M_STO3_ADC_L1_SFT		14
550 #define RT5677_M_STO2_ADC_L1			(0x1 << 14)
551 #define RT5677_M_STO2_ADC_L1_SFT		14
570 #define RT5677_M_STO1_ADC_L1			(0x1 << 14)
571 #define RT5677_M_STO1_ADC_L1_SFT		14
586 #define RT5677_M_MONO_ADC_L1			(0x1 << 14)
587 #define RT5677_M_MONO_ADC_L1_SFT		14
608 #define RT5677_M_DAC1_L				(0x1 << 14)
609 #define RT5677_M_DAC1_L_SFT			14
682 #define RT5677_STO_L_DD1_L_VOL_MASK		(0x1 << 14)
683 #define RT5677_STO_L_DD1_L_VOL_SFT		14
716 #define RT5677_STO_L_DD2_L_VOL_MASK		(0x1 << 14)
717 #define RT5677_STO_L_DD2_L_VOL_SFT		14
827 #define RT5677_DMIC_2_EN_MASK			(0x1 << 14)
828 #define RT5677_DMIC_2_EN_SFT			14
829 #define RT5677_DMIC_2_DIS			(0x0 << 14)
830 #define RT5677_DMIC_2_EN			(0x1 << 14)
915 #define RT5677_PWR_I2S2				(0x1 << 14)
916 #define RT5677_PWR_I2S2_BIT			14
943 #define RT5677_PWR_ADC_MF_L			(0x1 << 14)
944 #define RT5677_PWR_ADC_MF_L_BIT			14
975 #define RT5677_PWR_FV1				(0x1 << 14)
976 #define RT5677_PWR_FV1_BIT			14
999 #define RT5677_PWR_BST2				(0x1 << 14)
1000 #define RT5677_PWR_BST2_BIT			14
1272 #define RT5677_SCLK_SRC_MASK			(0x3 << 14)
1273 #define RT5677_SCLK_SRC_SFT			14
1274 #define RT5677_SCLK_SRC_MCLK			(0x0 << 14)
1275 #define RT5677_SCLK_SRC_PLL1			(0x1 << 14)
1276 #define RT5677_SCLK_SRC_RCCLK			(0x2 << 14) /* 25MHz */
1277 #define RT5677_SCLK_SRC_SLIM			(0x3 << 14)
1374 #define RT5677_DSP_IB_23_H			(0x1 << 14)
1375 #define RT5677_DSP_IB_23_H_SFT			14