Lines Matching full:12

325 #define RT5677_LOUT2_L_DF			(0x1 << 12)
326 #define RT5677_LOUT2_L_DF_SFT			(12)
339 #define RT5677_BST_MASK1			(0xf << 12)
340 #define RT5677_BST_SFT1				12
384 #define RT5677_ST_HPF_PATH			(0x1 << 12)
385 #define RT5677_ST_HPF_PATH_SFT			12
400 #define RT5677_SEL_DAC4_L_SRC_MASK		(0x7 << 12)
401 #define RT5677_SEL_DAC4_L_SRC_SFT		12
464 #define RT5677_STO1_ADC_R_BST_MASK		(0x3 << 12)
465 #define RT5677_STO1_ADC_R_BST_SFT		12
484 #define RT5677_MONO_ADC_R_BST_MASK		(0x3 << 12)
485 #define RT5677_MONO_ADC_R_BST_SFT		12
492 #define RT5677_STO3_ADC_R_BST_MASK		(0x3 << 12)
493 #define RT5677_STO3_ADC_R_BST_SFT		12
520 #define RT5677_SEL_STO4_ADC1_MASK		(0x3 << 12)
521 #define RT5677_SEL_STO4_ADC1_SFT		12
536 #define RT5677_SEL_STO3_ADC1_MASK		(0x3 << 12)
537 #define RT5677_SEL_STO3_ADC1_SFT		12
552 #define RT5677_SEL_STO2_ADC1_MASK		(0x3 << 12)
553 #define RT5677_SEL_STO2_ADC1_SFT		12
572 #define RT5677_SEL_STO1_ADC1_MASK		(0x3 << 12)
573 #define RT5677_SEL_STO1_ADC1_SFT		12
588 #define RT5677_SEL_MONO_ADC_L1_MASK		(0x3 << 12)
589 #define RT5677_SEL_MONO_ADC_L1_SFT		12
624 #define RT5677_DAC1_L_STO_L_VOL_MASK		(0x1 << 12)
625 #define RT5677_DAC1_L_STO_L_VOL_SFT		12
654 #define RT5677_DAC2_L_MONO_L_VOL_MASK		(0x1 << 12)
655 #define RT5677_DAC2_L_MONO_L_VOL_SFT		12
686 #define RT5677_MONO_L_DD1_L_VOL_MASK		(0x1 << 12)
687 #define RT5677_MONO_L_DD1_L_VOL_SFT		12
720 #define RT5677_MONO_L_DD2_L_VOL_MASK		(0x1 << 12)
721 #define RT5677_MONO_L_DD2_L_VOL_SFT		12
766 #define RT5677_SEL_PDM1_L_MASK			(0x3 << 12)
767 #define RT5677_SEL_PDM1_L_SFT			12
791 #define RT5677_PDM1_I2C_ID			(0xf << 12)
835 #define RT5677_DMIC_R_STO1_LH_MASK		(0x1 << 12)
836 #define RT5677_DMIC_R_STO1_LH_SFT		12
837 #define RT5677_DMIC_R_STO1_LH_FALLING		(0x0 << 12)
838 #define RT5677_DMIC_R_STO1_LH_RISING		(0x1 << 12)
919 #define RT5677_PWR_DAC1				(0x1 << 12)
920 #define RT5677_PWR_DAC1_BIT			12
947 #define RT5677_PWR_DAC_S1F			(0x1 << 12)
948 #define RT5677_PWR_DAC_S1F_BIT			12
979 #define RT5677_PWR_LO1				(0x1 << 12)
980 #define RT5677_PWR_LO1_BIT			12
1003 #define RT5677_PWR_SLIM				(0x1 << 12)
1004 #define RT5677_PWR_SLIM_BIT			12
1133 #define RT5677_I2S_PD1_MASK			(0x7 << 12)
1134 #define RT5677_I2S_PD1_SFT			12
1135 #define RT5677_I2S_PD1_1			(0x0 << 12)
1136 #define RT5677_I2S_PD1_2			(0x1 << 12)
1137 #define RT5677_I2S_PD1_3			(0x2 << 12)
1138 #define RT5677_I2S_PD1_4			(0x3 << 12)
1139 #define RT5677_I2S_PD1_6			(0x4 << 12)
1140 #define RT5677_I2S_PD1_8			(0x5 << 12)
1141 #define RT5677_I2S_PD1_12			(0x6 << 12)
1142 #define RT5677_I2S_PD1_16			(0x7 << 12)
1187 #define RT5677_I2S_PD5_MASK			(0x7 << 12)
1188 #define RT5677_I2S_PD5_SFT			12
1189 #define RT5677_I2S_PD5_1			(0x0 << 12)
1190 #define RT5677_I2S_PD5_2			(0x1 << 12)
1191 #define RT5677_I2S_PD5_3			(0x2 << 12)
1192 #define RT5677_I2S_PD5_4			(0x3 << 12)
1193 #define RT5677_I2S_PD5_6			(0x4 << 12)
1194 #define RT5677_I2S_PD5_8			(0x5 << 12)
1195 #define RT5677_I2S_PD5_12			(0x6 << 12)
1196 #define RT5677_I2S_PD5_16			(0x7 << 12)
1266 #define RT5677_PLL_M_MASK			(RT5677_PLL_M_MAX << 12)
1267 #define RT5677_PLL_M_SFT			12
1311 #define RT5677_PLL2_SRC_MASK			(0x7 << 12)
1312 #define RT5677_PLL2_SRC_SFT			12
1313 #define RT5677_PLL2_SRC_MCLK			(0x0 << 12)
1314 #define RT5677_PLL2_SRC_BCLK1			(0x1 << 12)
1315 #define RT5677_PLL2_SRC_BCLK2			(0x2 << 12)
1316 #define RT5677_PLL2_SRC_BCLK3			(0x3 << 12)
1317 #define RT5677_PLL2_SRC_BCLK4			(0x4 << 12)
1318 #define RT5677_PLL2_SRC_RCCLK			(0x5 << 12)
1319 #define RT5677_PLL2_SRC_SLIM			(0x6 << 12)
1342 #define RT5677_IB01_SRC_MASK			(0x7 << 12)
1343 #define RT5677_IB01_SRC_SFT			12
1352 #define RT5677_IB7_SRC_MASK			(0x7 << 12)
1353 #define RT5677_IB7_SRC_SFT			12
1378 #define RT5677_DSP_IB_6_H			(0x1 << 12)
1379 #define RT5677_DSP_IB_6_H_SFT			12