Lines Matching +full:6 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * max98090.h -- MAX98090 ALSA SoC Audio driver
66 /* MAX98090 Registers Bit Fields */
71 #define M98090_SWRESET_MASK BIT(7)
76 #define M98090_SR_96K_MASK BIT(5)
79 #define M98090_SR_32K_MASK BIT(4)
82 #define M98090_SR_48K_MASK BIT(3)
85 #define M98090_SR_44K1_MASK BIT(2)
88 #define M98090_SR_16K_MASK BIT(1)
91 #define M98090_SR_8K_MASK BIT(0)
97 #define M98090_SR_ALL_NUM BIT(M98090_SR_ALL_WIDTH)
102 #define M98090_RJ_M_MASK BIT(5)
105 #define M98090_RJ_S_MASK BIT(4)
108 #define M98090_LJ_M_MASK BIT(3)
111 #define M98090_LJ_S_MASK BIT(2)
114 #define M98090_I2S_M_MASK BIT(1)
117 #define M98090_I2S_S_MASK BIT(0)
122 #define M98090_DAI_ALL_NUM BIT(M98090_DAI_ALL_WIDTH)
127 #define M98090_DIG2_HP_MASK BIT(7)
130 #define M98090_DIG2_EAR_MASK BIT(6)
131 #define M98090_DIG2_EAR_SHIFT 6
133 #define M98090_DIG2_SPK_MASK BIT(5)
136 #define M98090_DIG2_LOUT_MASK BIT(4)
141 #define M98090_DIG2_ALL_NUM BIT(M98090_DIG2_ALL_WIDTH)
151 #define M98090_MBVSEL_2V4 BIT(0)
160 #define M98090_DIGMIC4_MASK BIT(3)
163 #define M98090_DIGMIC4_NUM BIT(M98090_DIGMIC4_WIDTH)
164 #define M98090_DIGMIC3_MASK BIT(2)
167 #define M98090_DIGMIC3_NUM BIT(M98090_DIGMIC3_WIDTH)
168 #define M98090_DIGMICR_MASK BIT(1)
171 #define M98090_DIGMICR_NUM BIT(M98090_DIGMICR_WIDTH)
172 #define M98090_DIGMICL_MASK BIT(0)
175 #define M98090_DIGMICL_NUM BIT(M98090_DIGMICL_WIDTH)
183 #define M98090_DMIC_COMP_NUM BIT(M98090_DMIC_COMP_WIDTH)
195 #define M98090_PSCLK_DIV1 BIT(4)
202 #define M98090_RJ_MASK BIT(5)
205 #define M98090_WCI_MASK BIT(4)
208 #define M98090_BCI_MASK BIT(3)
211 #define M98090_DLY_MASK BIT(2)
217 #define M98090_WS_NUM BIT(M98090_WS_WIDTH)
220 #define M98090_LTEN_MASK BIT(5)
223 #define M98090_LTEN_NUM BIT(M98090_LTEN_WIDTH)
224 #define M98090_LBEN_MASK BIT(4)
227 #define M98090_LBEN_NUM BIT(M98090_LBEN_WIDTH)
228 #define M98090_DMONO_MASK BIT(3)
231 #define M98090_DMONO_NUM BIT(M98090_DMONO_WIDTH)
232 #define M98090_HIZOFF_MASK BIT(2)
235 #define M98090_HIZOFF_NUM BIT(M98090_HIZOFF_WIDTH)
236 #define M98090_SDOEN_MASK BIT(1)
239 #define M98090_SDOEN_NUM BIT(M98090_SDOEN_WIDTH)
240 #define M98090_SDIEN_MASK BIT(0)
243 #define M98090_SDIEN_NUM BIT(M98090_SDIEN_WIDTH)
248 #define M98090_MODE_MASK BIT(7)
251 #define M98090_AHPF_MASK BIT(6)
252 #define M98090_AHPF_SHIFT 6
254 #define M98090_AHPF_NUM BIT(M98090_AHPF_WIDTH)
255 #define M98090_DHPF_MASK BIT(5)
258 #define M98090_DHPF_NUM BIT(M98090_DHPF_WIDTH)
259 #define M98090_DHF_MASK BIT(4)
262 #define M98090_FLT_DMIC34MODE_MASK BIT(3)
265 #define M98090_FLT_DMIC34HPF_MASK BIT(2)
268 #define M98090_FLT_DMIC34HPF_NUM BIT(M98090_FLT_DMIC34HPF_WIDTH)
276 #define M98090_USE_M1_MASK BIT(0)
279 #define M98090_USE_M1_NUM BIT(M98090_USE_M1_WIDTH)
284 #define M98090_MIXHPL_MIC2_MASK BIT(5)
287 #define M98090_MIXHPL_MIC1_MASK BIT(4)
290 #define M98090_MIXHPL_LINEB_MASK BIT(3)
293 #define M98090_MIXHPL_LINEA_MASK BIT(2)
296 #define M98090_MIXHPL_DACR_MASK BIT(1)
299 #define M98090_MIXHPL_DACL_MASK BIT(0)
304 #define M98090_MIXHPL_WIDTH 6
309 #define M98090_MIXHPR_MIC2_MASK BIT(5)
312 #define M98090_MIXHPR_MIC1_MASK BIT(4)
315 #define M98090_MIXHPR_LINEB_MASK BIT(3)
318 #define M98090_MIXHPR_LINEA_MASK BIT(2)
321 #define M98090_MIXHPR_DACR_MASK BIT(1)
324 #define M98090_MIXHPR_DACL_MASK BIT(0)
329 #define M98090_MIXHPR_WIDTH 6
334 #define M98090_HPLM_MASK BIT(7)
340 #define M98090_HPVOLL_NUM BIT(M98090_HPVOLL_WIDTH)
345 #define M98090_HPRM_MASK BIT(7)
351 #define M98090_HPVOLR_NUM BIT(M98090_HPVOLR_WIDTH)
356 #define M98090_MIXSPL_MIC2_MASK BIT(5)
359 #define M98090_MIXSPL_MIC1_MASK BIT(4)
362 #define M98090_MIXSPL_LINEB_MASK BIT(3)
365 #define M98090_MIXSPL_LINEA_MASK BIT(2)
368 #define M98090_MIXSPL_DACR_MASK BIT(1)
371 #define M98090_MIXSPL_DACL_MASK BIT(0)
376 #define M98090_MIXSPL_WIDTH 6
377 #define M98090_MIXSPR_DACR_MASK BIT(1)
384 #define M98090_SPK_SLAVE_MASK BIT(6)
385 #define M98090_SPK_SLAVE_SHIFT 6
387 #define M98090_MIXSPR_MIC2_MASK BIT(5)
390 #define M98090_MIXSPR_MIC1_MASK BIT(4)
393 #define M98090_MIXSPR_LINEB_MASK BIT(3)
396 #define M98090_MIXSPR_LINEA_MASK BIT(2)
399 #define M98090_MIXSPR_DACR_MASK BIT(1)
402 #define M98090_MIXSPR_DACL_MASK BIT(0)
407 #define M98090_MIXSPR_WIDTH 6
412 #define M98090_SPLM_MASK BIT(7)
417 #define M98090_SPVOLL_WIDTH 6
423 #define M98090_SPRM_MASK BIT(7)
428 #define M98090_SPVOLR_WIDTH 6
434 #define M98090_MIXRCVL_MIC2_MASK BIT(5)
437 #define M98090_MIXRCVL_MIC1_MASK BIT(4)
440 #define M98090_MIXRCVL_LINEB_MASK BIT(3)
443 #define M98090_MIXRCVL_LINEA_MASK BIT(2)
446 #define M98090_MIXRCVL_DACR_MASK BIT(1)
449 #define M98090_MIXRCVL_DACL_MASK BIT(0)
454 #define M98090_MIXRCVL_WIDTH 6
462 #define M98090_MIXRCVLG_NUM BIT(M98090_MIXRCVLG_WIDTH)
467 #define M98090_RCVLM_MASK BIT(7)
473 #define M98090_RCVLVOL_NUM BIT(M98090_RCVLVOL_WIDTH)
478 #define M98090_LINMOD_MASK BIT(7)
481 #define M98090_MIXRCVR_MIC2_MASK BIT(5)
484 #define M98090_MIXRCVR_MIC1_MASK BIT(4)
487 #define M98090_MIXRCVR_LINEB_MASK BIT(3)
490 #define M98090_MIXRCVR_LINEA_MASK BIT(2)
493 #define M98090_MIXRCVR_DACR_MASK BIT(1)
496 #define M98090_MIXRCVR_DACL_MASK BIT(0)
501 #define M98090_MIXRCVR_WIDTH 6
506 #define M98090_RCVRM_MASK BIT(7)
512 #define M98090_RCVRVOL_NUM BIT(M98090_RCVRVOL_WIDTH)
517 #define M98090_JDETEN_MASK BIT(7)
520 #define M98090_JDWK_MASK BIT(6)
521 #define M98090_JDWK_SHIFT 6
527 #define M98090_JDEB_50MS BIT(0)
534 #define M98090_MBEN_MASK BIT(4)
537 #define M98090_LINEAEN_MASK BIT(3)
540 #define M98090_LINEBEN_MASK BIT(2)
543 #define M98090_ADREN_MASK BIT(1)
546 #define M98090_ADLEN_MASK BIT(0)
553 #define M98090_HPREN_MASK BIT(7)
556 #define M98090_HPLEN_MASK BIT(6)
557 #define M98090_HPLEN_SHIFT 6
559 #define M98090_SPREN_MASK BIT(5)
562 #define M98090_SPLEN_MASK BIT(4)
565 #define M98090_RCVLEN_MASK BIT(3)
568 #define M98090_RCVREN_MASK BIT(2)
571 #define M98090_DAREN_MASK BIT(1)
574 #define M98090_DALEN_MASK BIT(0)
581 #define M98090_ZDENN_MASK BIT(2)
584 #define M98090_ZDENN_NUM BIT(M98090_ZDENN_WIDTH)
585 #define M98090_VS2ENN_MASK BIT(1)
588 #define M98090_VS2ENN_NUM BIT(M98090_VS2ENN_WIDTH)
589 #define M98090_VSENN_MASK BIT(0)
592 #define M98090_VSENN_NUM BIT(M98090_VSENN_WIDTH)
597 #define M98090_VCM_MODE_MASK BIT(0)
600 #define M98090_VCM_MODE_NUM BIT(M98090_VCM_MODE_WIDTH)
605 #define M98090_PERFMODE_MASK BIT(1)
608 #define M98090_PERFMODE_NUM BIT(M98090_PERFMODE_WIDTH)
609 #define M98090_DACHP_MASK BIT(0)
612 #define M98090_DACHP_NUM BIT(M98090_DACHP_WIDTH)
617 #define M98090_OSR128_MASK BIT(2)
620 #define M98090_ADCDITHER_MASK BIT(1)
623 #define M98090_ADCDITHER_NUM BIT(M98090_ADCDITHER_WIDTH)
624 #define M98090_ADCHP_MASK BIT(0)
627 #define M98090_ADCHP_NUM BIT(M98090_ADCHP_WIDTH)
632 #define M98090_SHDNN_MASK BIT(7)
642 #define M98090_REVID_NUM BIT(M98090_REVID_WIDTH)
654 * @returns -1 for error and 0 Success.