1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/imx-regs.h>
28 #define UCR1_RRDYEN	(1<<9)	/* Recv ready interrupt enable */
29 #define UCR1_RDMAEN	(1<<8)	/* Recv ready DMA enable */
31 #define UCR1_TXMPTYEN	(1<<6)	/* Transimitter empty interrupt enable */
74 #define UCR4_DREN	(1<<0)  /* Recv data ready interrupt enable */
93 #define USR2_TXFE	(1<<14) /* Transmit buffer FIFO empty */
102 #define USR2_RDR	(1<<0)	/* Recv data ready */
105 #define UTS_TXEMPTY	(1<<6)	/* TxFIFO empty */
106 #define UTS_RXEMPTY	(1<<5)	/* RxFIFO empty */
143 	writel(0, &base->cr1);  in _mxc_serial_init()
144 	writel(0, &base->cr2);  in _mxc_serial_init()
146 	while (!(readl(&base->cr2) & UCR2_SRST));  in _mxc_serial_init()
149 		writel(0x404 | UCR3_ADNIMP, &base->cr3);  in _mxc_serial_init()
151 		writel(0x704 | UCR3_ADNIMP, &base->cr3);  in _mxc_serial_init()
153 	writel(0x704 | UCR3_ADNIMP, &base->cr3);  in _mxc_serial_init()
154 	writel(0x8000, &base->cr4);  in _mxc_serial_init()
155 	writel(0x2b, &base->esc);  in _mxc_serial_init()
156 	writel(0, &base->tim);  in _mxc_serial_init()
158 	writel(0, &base->ts);  in _mxc_serial_init()
171 	writel(tmp, &base->fcr);  in _mxc_serial_setbrg()
173 	writel(0xf, &base->bir);  in _mxc_serial_setbrg()
174 	writel(clk / (2 * baudrate), &base->bmr);  in _mxc_serial_setbrg()
177 	       &base->cr2);  in _mxc_serial_setbrg()
178 	writel(UCR1_UARTEN, &base->cr1);  in _mxc_serial_setbrg()
193 	if (!gd->baudrate)  in mxc_serial_setbrg()
194 		gd->baudrate = CONFIG_BAUDRATE;  in mxc_serial_setbrg()
196 	_mxc_serial_setbrg(mxc_base, clk, gd->baudrate, false);  in mxc_serial_setbrg()
201 	while (readl(&mxc_base->ts) & UTS_RXEMPTY)  in mxc_serial_getc()
203 	return (readl(&mxc_base->rxd) & URXD_RX_DATA); /* mask out status from upper word */  in mxc_serial_getc()
212 	writel(c, &mxc_base->txd);  in mxc_serial_putc()
215 	while (!(readl(&mxc_base->ts) & UTS_TXEMPTY))  in mxc_serial_putc()
222 	/* If receive fifo is empty, return false */  in mxc_serial_tstc()
223 	if (readl(&mxc_base->ts) & UTS_RXEMPTY)  in mxc_serial_tstc()
267 	struct mxc_serial_platdata *plat = dev->platdata;  in mxc_serial_setbrg()
270 	_mxc_serial_setbrg(plat->reg, clk, baudrate, plat->use_dte);  in mxc_serial_setbrg()
277 	struct mxc_serial_platdata *plat = dev->platdata;  in mxc_serial_probe()
279 	_mxc_serial_init(plat->reg, plat->use_dte);  in mxc_serial_probe()
286 	struct mxc_serial_platdata *plat = dev->platdata;  in mxc_serial_getc()
287 	struct mxc_uart *const uart = plat->reg;  in mxc_serial_getc()
289 	if (readl(&uart->ts) & UTS_RXEMPTY)  in mxc_serial_getc()
290 		return -EAGAIN;  in mxc_serial_getc()
292 	return readl(&uart->rxd) & URXD_RX_DATA;  in mxc_serial_getc()
297 	struct mxc_serial_platdata *plat = dev->platdata;  in mxc_serial_putc()
298 	struct mxc_uart *const uart = plat->reg;  in mxc_serial_putc()
300 	if (!(readl(&uart->ts) & UTS_TXEMPTY))  in mxc_serial_putc()
301 		return -EAGAIN;  in mxc_serial_putc()
303 	writel(ch, &uart->txd);  in mxc_serial_putc()
310 	struct mxc_serial_platdata *plat = dev->platdata;  in mxc_serial_pending()
311 	struct mxc_uart *const uart = plat->reg;  in mxc_serial_pending()
312 	uint32_t sr2 = readl(&uart->sr2);  in mxc_serial_pending()
330 	struct mxc_serial_platdata *plat = dev->platdata;  in mxc_serial_ofdata_to_platdata()
335 		return -EINVAL;  in mxc_serial_ofdata_to_platdata()
337 	plat->reg = (struct mxc_uart *)addr;  in mxc_serial_ofdata_to_platdata()
339 	plat->use_dte = fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev),  in mxc_serial_ofdata_to_platdata()
340 					"fsl,dte-mode");  in mxc_serial_ofdata_to_platdata()
345 	{ .compatible = "fsl,imx6ul-uart" },
346 	{ .compatible = "fsl,imx7d-uart" },
347 	{ .compatible = "fsl,imx6q-uart" },
384 	while (!(readl(&base->ts) & UTS_TXEMPTY))  in _debug_uart_putc()
387 	writel(ch, &base->txd);  in _debug_uart_putc()