ram/stm32mp1/stm32mp1_ddr_regs.h

1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3  * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
13 	u8 reserved008[0x10 - 0x8];
20 	u8 reserved028[0x30 - 0x28];
22 	u32 pwrtmg;		/* 0x34 Low Power Timing*/
24 	u8 reserved03c[0x50 - 0x3C];
30 	u32 rfshtmg;		/* 0x64 Refresh Timing*/
31 	u8 reserved068[0xc0 - 0x68];
45 	u8 reserved0f4[0x100 - 0xf4];
46 	u32 dramtmg0;		/* 0x100 SDRAM Timing 0*/
47 	u32 dramtmg1;		/* 0x104 SDRAM Timing 1*/
48 	u32 dramtmg2;		/* 0x108 SDRAM Timing 2*/
49 	u32 dramtmg3;		/* 0x10c SDRAM Timing 3*/
50 	u32 dramtmg4;		/* 0x110 SDRAM Timing 4*/
51 	u32 dramtmg5;		/* 0x114 SDRAM Timing 5*/
52 	u32 dramtmg6;		/* 0x118 SDRAM Timing 6*/
53 	u32 dramtmg7;		/* 0x11c SDRAM Timing 7*/
54 	u32 dramtmg8;		/* 0x120 SDRAM Timing 8*/
55 	u8 reserved124[0x138 - 0x124];
56 	u32 dramtmg14;		/* 0x138 SDRAM Timing 14*/
57 	u32 dramtmg15;		/* 0x13C SDRAM Timing 15*/
58 	u8 reserved140[0x180 - 0x140];
63 	u32 dfitmg0;		/* 0x190 DFI Timing 0*/
64 	u32 dfitmg1;		/* 0x194 DFI Timing 1*/
72 	u8 reserved1b4[0x1bc - 0x1b4];
74 	u8 reserved1c0[0x1c4 - 0x1c0];
76 	u8 reserved1c8[0x204 - 0x1c8];
83 	u8 reserved21c[0x224 - 0x21c];
87 	u8 reserved230[0x240 - 0x230];
90 	u8 reserved248[0x250 - 0x248];
99 	u8 reserved27c[0x300 - 0x270];
105 	u8 reserved314[0x320 - 0x314];
108 	u8 reserved328[0x36c - 0x328];
111 	u8 reserved374[0x3fc - 0x374];
120 	u8 reserved40c[0x490 - 0x40c];
126 	u8 reserved4a4[0x4b4 - 0x4a4];
131 	u8 reserved4bc[0x540 - 0x4bc];
147 	u32 ptr0;		/* 0x18 R/W PHY Timing 0*/
148 	u32 ptr1;		/* 0x1C R/W PHY Timing 1*/
149 	u32 ptr2;		/* 0x20 R/W PHY Timing 2*/
154 	u32 dtpr0;		/* 0x34 DRAM Timing Parameters0*/
155 	u32 dtpr1;		/* 0x38 DRAM Timing Parameters1*/
156 	u32 dtpr2;		/* 0x3C DRAM Timing Parameters2*/
165 	u8 res1[0x0c0 - 0x060];	/* 0x60 */
171 	u32 dcutpr;		/* 0xd4 DCU Timing Parameters */
174 	u8 res2[0x100 - 0xe0];	/* 0xe0 */
192 	u8 res3[0x178 - 0x144];	/* 0x144 */
199 	u8 res4[0x1C0 - 0x190];	/* 0x190 */
204 	u32 dx0dqtr;		/* 0x1d0 Byte lane 0 DQ Timing*/
205 	u32 dx0dqstr;		/* 0x1d4 Byte lane 0 DQS Timing*/
206 	u8 res5[0x200 - 0x1d8];	/* 0x1d8 */
211 	u32 dx1dqtr;		/* 0x210 Byte lane 1 DQ Timing*/
212 	u32 dx1dqstr;		/* 0x214 Byte lane 1 QS Timing*/
213 	u8 res6[0x240 - 0x218];	/* 0x218 */
218 	u32 dx2dqtr;		/* 0x250 Byte lane 2 DQ Timing*/
219 	u32 dx2dqstr;		/* 0x254 Byte lane 2 QS Timing*/
220 	u8 res7[0x280 - 0x258];	/* 0x258 */
225 	u32 dx3dqtr;		/* 0x290 Byte lane 3 DQ Timing*/
226 	u32 dx3dqstr;		/* 0x294 Byte lane 3 QS Timing*/