Lines Matching +full:rk3399 +full:- +full:pmucru
1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * (C) Copyright 2016-2017 Rockchip Inc.
11 #include <dt-structs.h>
37 struct rk3399_pmucru *pmucru; member
83 u32 *denali_phy = ddr_publ_regs->denali_phy; in phy_dll_bypass_set()
115 &sdram_params->ch[channel]; in set_memory_map()
116 u32 *denali_ctl = chan->pctl->denali_ctl; in set_memory_map()
117 u32 *denali_pi = chan->pi->denali_pi; in set_memory_map()
123 if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4) in set_memory_map()
125 else if (sdram_ch->ddrconfig == 3) in set_memory_map()
130 cs_map = (sdram_ch->rank > 1) ? 3 : 1; in set_memory_map()
131 reduc = (sdram_ch->bw == 2) ? 0 : 1; in set_memory_map()
134 clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); in set_memory_map()
136 ((3 - sdram_ch->bk) << 16) | in set_memory_map()
137 ((16 - row) << 24)); in set_memory_map()
143 clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col)); in set_memory_map()
147 ((3 - sdram_ch->bk) << 16) | in set_memory_map()
148 ((16 - row) << 24)); in set_memory_map()
151 if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3)) in set_memory_map()
158 u32 *denali_phy = chan->publ->denali_phy; in set_ds_odt()
166 if (sdram_params->base.dramtype == LPDDR4) { in set_ds_odt()
176 } else if (sdram_params->base.dramtype == LPDDR3) { in set_ds_odt()
198 if (sdram_params->base.odt == 1) in set_ds_odt()
297 u32 *denali_phy = chan->publ->denali_phy; in phy_io_config()
305 if (sdram_params->base.dramtype == LPDDR4) { in phy_io_config()
311 } else if (sdram_params->base.dramtype == LPDDR3) { in phy_io_config()
312 if (sdram_params->base.odt == 1) { in phy_io_config()
329 return -EINVAL; in phy_io_config()
344 return -EINVAL; in phy_io_config()
359 return -EINVAL; in phy_io_config()
363 return -EINVAL; in phy_io_config()
371 } else if (sdram_params->base.dramtype == DDR3) { in phy_io_config()
379 return -EINVAL; in phy_io_config()
398 if (sdram_params->base.dramtype == LPDDR4) in phy_io_config()
400 else if (sdram_params->base.dramtype == LPDDR3) in phy_io_config()
402 else if (sdram_params->base.dramtype == DDR3) in phy_io_config()
405 return -EINVAL; in phy_io_config()
426 if (sdram_params->base.ddr_freq < 400) in phy_io_config()
428 else if (sdram_params->base.ddr_freq < 800) in phy_io_config()
430 else if (sdram_params->base.ddr_freq < 1200) in phy_io_config()
458 u32 *denali_ctl = chan->pctl->denali_ctl; in pctl_cfg()
459 u32 *denali_pi = chan->pi->denali_pi; in pctl_cfg()
460 u32 *denali_phy = chan->publ->denali_phy; in pctl_cfg()
461 const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl; in pctl_cfg()
462 const u32 *params_phy = sdram_params->phy_regs.denali_phy; in pctl_cfg()
473 sizeof(struct rk3399_ddr_pctl_regs) - 4); in pctl_cfg()
475 copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0], in pctl_cfg()
480 writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]); in pctl_cfg()
481 writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]); in pctl_cfg()
482 writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]); in pctl_cfg()
505 copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4); in pctl_cfg()
506 copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4); in pctl_cfg()
507 copy_to_reg(&denali_phy[128], ¶ms_phy[128], (218 - 128 + 1) * 4); in pctl_cfg()
508 copy_to_reg(&denali_phy[256], ¶ms_phy[256], (346 - 256 + 1) * 4); in pctl_cfg()
509 copy_to_reg(&denali_phy[384], ¶ms_phy[384], (474 - 384 + 1) * 4); in pctl_cfg()
510 copy_to_reg(&denali_phy[512], ¶ms_phy[512], (549 - 512 + 1) * 4); in pctl_cfg()
511 copy_to_reg(&denali_phy[640], ¶ms_phy[640], (677 - 640 + 1) * 4); in pctl_cfg()
512 copy_to_reg(&denali_phy[768], ¶ms_phy[768], (805 - 768 + 1) * 4); in pctl_cfg()
554 return -ETIME; in pctl_cfg()
567 u32 *denali_phy = chan->publ->denali_phy; in select_per_cs_training_index()
584 u32 *denali_ctl = chan->pctl->denali_ctl; in override_write_leveling_value()
585 u32 *denali_phy = chan->publ->denali_phy; in override_write_leveling_value()
614 u32 *denali_pi = chan->pi->denali_pi; in data_training_ca()
615 u32 *denali_phy = chan->publ->denali_phy; in data_training_ca()
618 u32 rank = sdram_params->ch[channel].rank; in data_training_ca()
651 return -EIO; in data_training_ca()
664 u32 *denali_pi = chan->pi->denali_pi; in data_training_wl()
665 u32 *denali_phy = chan->publ->denali_phy; in data_training_wl()
668 u32 rank = sdram_params->ch[channel].rank; in data_training_wl()
705 return -EIO; in data_training_wl()
720 u32 *denali_pi = chan->pi->denali_pi; in data_training_rg()
721 u32 *denali_phy = chan->publ->denali_phy; in data_training_rg()
724 u32 rank = sdram_params->ch[channel].rank; in data_training_rg()
764 return -EIO; in data_training_rg()
777 u32 *denali_pi = chan->pi->denali_pi; in data_training_rl()
779 u32 rank = sdram_params->ch[channel].rank; in data_training_rl()
805 return -EIO; in data_training_rl()
818 u32 *denali_pi = chan->pi->denali_pi; in data_training_wdql()
820 u32 rank = sdram_params->ch[channel].rank; in data_training_wdql()
845 return -EIO; in data_training_wdql()
859 u32 *denali_phy = chan->publ->denali_phy; in data_training()
865 if (sdram_params->base.dramtype == LPDDR4) { in data_training()
869 } else if (sdram_params->base.dramtype == LPDDR3) { in data_training()
872 } else if (sdram_params->base.dramtype == DDR3) { in data_training()
910 struct rk3399_msch_regs *ddr_msch_regs = chan->msch; in set_ddrconfig()
914 cs0_cap = (1 << (sdram_params->ch[channel].cs0_row in set_ddrconfig()
915 + sdram_params->ch[channel].col in set_ddrconfig()
916 + sdram_params->ch[channel].bk in set_ddrconfig()
917 + sdram_params->ch[channel].bw - 20)); in set_ddrconfig()
918 if (sdram_params->ch[channel].rank > 1) in set_ddrconfig()
919 cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row in set_ddrconfig()
920 - sdram_params->ch[channel].cs1_row); in set_ddrconfig()
921 if (sdram_params->ch[channel].row_3_4) { in set_ddrconfig()
926 writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf); in set_ddrconfig()
928 &ddr_msch_regs->ddrsize); in set_ddrconfig()
937 sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; in dram_all_config()
938 sys_reg |= (sdram_params->base.num_channels - 1) in dram_all_config()
941 (idx < sdram_params->base.num_channels) && (channel < 2); in dram_all_config()
944 &sdram_params->ch[channel]; in dram_all_config()
948 if (sdram_params->ch[channel].col == 0) in dram_all_config()
951 sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel); in dram_all_config()
953 sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel); in dram_all_config()
954 sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel); in dram_all_config()
955 sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel); in dram_all_config()
956 sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel); in dram_all_config()
957 sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel); in dram_all_config()
958 sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel); in dram_all_config()
959 sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel); in dram_all_config()
961 ddr_msch_regs = dram->chan[channel].msch; in dram_all_config()
962 noc_timing = &sdram_params->ch[channel].noc_timings; in dram_all_config()
963 writel(noc_timing->ddrtiminga0, in dram_all_config()
964 &ddr_msch_regs->ddrtiminga0); in dram_all_config()
965 writel(noc_timing->ddrtimingb0, in dram_all_config()
966 &ddr_msch_regs->ddrtimingb0); in dram_all_config()
967 writel(noc_timing->ddrtimingc0, in dram_all_config()
968 &ddr_msch_regs->ddrtimingc0); in dram_all_config()
969 writel(noc_timing->devtodev0, in dram_all_config()
970 &ddr_msch_regs->devtodev0); in dram_all_config()
971 writel(noc_timing->ddrmode, in dram_all_config()
972 &ddr_msch_regs->ddrmode); in dram_all_config()
975 if (sdram_params->ch[channel].rank == 1) in dram_all_config()
976 setbits_le32(&dram->chan[channel].pctl->denali_ctl[276], in dram_all_config()
980 writel(sys_reg, &dram->pmugrf->os_reg2); in dram_all_config()
981 rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10, in dram_all_config()
982 sdram_params->base.stride << 10); in dram_all_config()
987 &dram->pmucru->pmucru_rstnhold_con[1]); in dram_all_config()
988 clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3); in dram_all_config()
996 u32 ch_count = sdram_params->base.num_channels; in switch_to_phy_index1()
1002 &dram->cic->cic_ctrl0); in switch_to_phy_index1()
1003 while (!(readl(&dram->cic->cic_status0) & (1 << 2))) { in switch_to_phy_index1()
1008 return -ETIME; in switch_to_phy_index1()
1013 writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0); in switch_to_phy_index1()
1014 while (!(readl(&dram->cic->cic_status0) & (1 << 0))) { in switch_to_phy_index1()
1019 return -ETIME; in switch_to_phy_index1()
1024 denali_phy = dram->chan[channel].publ->denali_phy; in switch_to_phy_index1()
1026 ret = data_training(&dram->chan[channel], channel, in switch_to_phy_index1()
1040 unsigned char dramtype = sdram_params->base.dramtype; in sdram_init()
1041 unsigned int ddr_freq = sdram_params->base.ddr_freq; in sdram_init()
1050 return -E2BIG; in sdram_init()
1054 const struct chan_info *chan = &dram->chan[channel]; in sdram_init()
1055 struct rk3399_ddr_publ_regs *publ = chan->publ; in sdram_init()
1059 if (channel >= sdram_params->base.num_channels) in sdram_init()
1064 return -EIO; in sdram_init()
1074 return -EIO; in sdram_init()
1078 sdram_params->ch[channel].ddrconfig); in sdram_init()
1093 ret = dev_read_u32_array(dev, "rockchip,sdram-params", in rk3399_dmc_ofdata_to_platdata()
1094 (u32 *)&plat->sdram_params, in rk3399_dmc_ofdata_to_platdata()
1095 sizeof(plat->sdram_params) / sizeof(u32)); in rk3399_dmc_ofdata_to_platdata()
1097 printf("%s: Cannot read rockchip,sdram-params %d\n", in rk3399_dmc_ofdata_to_platdata()
1101 ret = regmap_init_mem(dev_ofnode(dev), &plat->map); in rk3399_dmc_ofdata_to_platdata()
1113 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; in conv_of_platdata()
1116 ret = regmap_init_mem_platdata(dev, dtplat->reg, in conv_of_platdata()
1117 ARRAY_SIZE(dtplat->reg) / 2, in conv_of_platdata()
1118 &plat->map); in conv_of_platdata()
1132 struct rk3399_sdram_params *params = &plat->sdram_params; in rk3399_dmc_init()
1134 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat; in rk3399_dmc_init()
1136 (void *)dtplat->rockchip_sdram_params; in rk3399_dmc_init()
1143 priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC); in rk3399_dmc_init()
1144 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); in rk3399_dmc_init()
1145 priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF); in rk3399_dmc_init()
1146 priv->pmucru = rockchip_get_pmucru(); in rk3399_dmc_init()
1147 priv->cru = rockchip_get_cru(); in rk3399_dmc_init()
1148 priv->chan[0].pctl = regmap_get_range(plat->map, 0); in rk3399_dmc_init()
1149 priv->chan[0].pi = regmap_get_range(plat->map, 1); in rk3399_dmc_init()
1150 priv->chan[0].publ = regmap_get_range(plat->map, 2); in rk3399_dmc_init()
1151 priv->chan[0].msch = regmap_get_range(plat->map, 3); in rk3399_dmc_init()
1152 priv->chan[1].pctl = regmap_get_range(plat->map, 4); in rk3399_dmc_init()
1153 priv->chan[1].pi = regmap_get_range(plat->map, 5); in rk3399_dmc_init()
1154 priv->chan[1].publ = regmap_get_range(plat->map, 6); in rk3399_dmc_init()
1155 priv->chan[1].msch = regmap_get_range(plat->map, 7); in rk3399_dmc_init()
1158 priv->chan[0].pctl, priv->chan[0].pi, in rk3399_dmc_init()
1159 priv->chan[0].publ, priv->chan[0].msch, in rk3399_dmc_init()
1160 priv->chan[1].pctl, priv->chan[1].pi, in rk3399_dmc_init()
1161 priv->chan[1].publ, priv->chan[1].msch); in rk3399_dmc_init()
1162 debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru, in rk3399_dmc_init()
1163 priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru); in rk3399_dmc_init()
1165 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk); in rk3399_dmc_init()
1167 ret = clk_get_by_index(dev, 0, &priv->ddr_clk); in rk3399_dmc_init()
1173 ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz); in rk3399_dmc_init()
1196 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF); in rk3399_dmc_probe()
1197 debug("%s: pmugrf=%p\n", __func__, priv->pmugrf); in rk3399_dmc_probe()
1198 priv->info.base = CONFIG_SYS_SDRAM_BASE; in rk3399_dmc_probe()
1199 priv->info.size = rockchip_sdram_size( in rk3399_dmc_probe()
1200 (phys_addr_t)&priv->pmugrf->os_reg2); in rk3399_dmc_probe()
1209 *info = priv->info; in rk3399_dmc_get_info()
1220 { .compatible = "rockchip,rk3399-dmc" },