130 	cs_map = (sdram_ch->rank > 1) ? 3 : 1;  in set_memory_map()
151 	if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3))  in set_memory_map()
477 	/* rank count need to set for init */  in pctl_cfg()
565 					 u32 rank)  in select_per_cs_training_index()  argument
575 		clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);  in select_per_cs_training_index()
576 		clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);  in select_per_cs_training_index()
577 		clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);  in select_per_cs_training_index()
578 		clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);  in select_per_cs_training_index()
618 	u32 rank = sdram_params->ch[channel].rank;  in data_training_ca()  local
620 	for (i = 0; i < rank; i++) {  in data_training_ca()
668 	u32 rank = sdram_params->ch[channel].rank;  in data_training_wl()  local
670 	for (i = 0; i < rank; i++) {  in data_training_wl()
724 	u32 rank = sdram_params->ch[channel].rank;  in data_training_rg()  local
726 	for (i = 0; i < rank; i++) {  in data_training_rg()
779 	u32 rank = sdram_params->ch[channel].rank;  in data_training_rl()  local
781 	for (i = 0; i < rank; i++) {  in data_training_rl()
820 	u32 rank = sdram_params->ch[channel].rank;  in data_training_wdql()  local
822 	for (i = 0; i < rank; i++) {  in data_training_wdql()
918 	if (sdram_params->ch[channel].rank > 1)  in set_ddrconfig()
953 		sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);  in dram_all_config()
974 		/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */  in dram_all_config()
975 		if (sdram_params->ch[channel].rank == 1)  in dram_all_config()