Lines Matching +full:buck +full:- +full:boost
1 // SPDX-License-Identifier: GPL-2.0+
18 * struct pfuze100_regulator_desc - regulator descriptor
43 * struct pfuze100_regulator_platdata - platform data for pfuze100
148 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000, -1
152 -1, -1, -1, -1, -1, -1, 3000000, -1
218 /* SWx Buck regulator mode */
231 /* Boost Buck regulator mode for normal operation */
252 if (!strcmp(desc->name, name)) in se_desc()
270 dev->name); in pfuze100_regulator_probe()
275 dev->name); in pfuze100_regulator_probe()
280 dev->name); in pfuze100_regulator_probe()
284 return -EINVAL; in pfuze100_regulator_probe()
287 debug("Do not support regulator %s\n", dev->name); in pfuze100_regulator_probe()
288 return -EINVAL; in pfuze100_regulator_probe()
291 plat->desc = desc; in pfuze100_regulator_probe()
294 uc_pdata->type = desc->type; in pfuze100_regulator_probe()
295 if (uc_pdata->type == REGULATOR_TYPE_BUCK) { in pfuze100_regulator_probe()
296 if (!strcmp(dev->name, "swbst")) { in pfuze100_regulator_probe()
297 uc_pdata->mode = pfuze_swbst_modes; in pfuze100_regulator_probe()
298 uc_pdata->mode_count = ARRAY_SIZE(pfuze_swbst_modes); in pfuze100_regulator_probe()
300 uc_pdata->mode = pfuze_sw_modes; in pfuze100_regulator_probe()
301 uc_pdata->mode_count = ARRAY_SIZE(pfuze_sw_modes); in pfuze100_regulator_probe()
303 } else if (uc_pdata->type == REGULATOR_TYPE_LDO) { in pfuze100_regulator_probe()
304 uc_pdata->mode = pfuze_ldo_modes; in pfuze100_regulator_probe()
305 uc_pdata->mode_count = ARRAY_SIZE(pfuze_ldo_modes); in pfuze100_regulator_probe()
307 uc_pdata->mode = NULL; in pfuze100_regulator_probe()
308 uc_pdata->mode_count = 0; in pfuze100_regulator_probe()
318 struct pfuze100_regulator_desc *desc = plat->desc; in pfuze100_regulator_mode()
321 if (desc->type == REGULATOR_TYPE_BUCK) { in pfuze100_regulator_mode()
322 if (!strcmp(dev->name, "swbst")) { in pfuze100_regulator_mode()
323 val = pmic_reg_read(dev->parent, in pfuze100_regulator_mode()
324 desc->vsel_reg); in pfuze100_regulator_mode()
334 val = pmic_reg_read(dev->parent, in pfuze100_regulator_mode()
335 desc->vsel_reg + in pfuze100_regulator_mode()
346 } else if (desc->type == REGULATOR_TYPE_LDO) { in pfuze100_regulator_mode()
347 val = pmic_reg_read(dev->parent, desc->vsel_reg); in pfuze100_regulator_mode()
357 return -EINVAL; in pfuze100_regulator_mode()
361 if (desc->type == REGULATOR_TYPE_BUCK) { in pfuze100_regulator_mode()
362 if (!strcmp(dev->name, "swbst")) in pfuze100_regulator_mode()
363 return pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_mode()
367 val = pmic_clrsetbits(dev->parent, in pfuze100_regulator_mode()
368 desc->vsel_reg + PFUZE100_MODE_OFFSET, in pfuze100_regulator_mode()
372 } else if (desc->type == REGULATOR_TYPE_LDO) { in pfuze100_regulator_mode()
373 val = pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_mode()
378 return -EINVAL; in pfuze100_regulator_mode()
392 if (!strcmp(dev->name, "vrefddr")) { in pfuze100_regulator_enable()
393 val = pmic_reg_read(dev->parent, PFUZE100_VREFDDRCON); in pfuze100_regulator_enable()
416 if (!strcmp(dev->name, "vrefddr")) { in pfuze100_regulator_enable()
417 val = pmic_reg_read(dev->parent, PFUZE100_VREFDDRCON); in pfuze100_regulator_enable()
425 return pmic_reg_write(dev->parent, PFUZE100_VREFDDRCON, in pfuze100_regulator_enable()
429 if (uc_pdata->type == REGULATOR_TYPE_LDO) { in pfuze100_regulator_enable()
431 } else if (uc_pdata->type == REGULATOR_TYPE_BUCK) { in pfuze100_regulator_enable()
432 if (!strcmp(dev->name, "swbst")) in pfuze100_regulator_enable()
438 return -EINVAL; in pfuze100_regulator_enable()
452 struct pfuze100_regulator_desc *desc = plat->desc; in pfuze100_regulator_val()
458 if (uc_pdata->type == REGULATOR_TYPE_FIXED) { in pfuze100_regulator_val()
459 *uV = desc->voltage; in pfuze100_regulator_val()
460 } else if (desc->volt_table) { in pfuze100_regulator_val()
461 val = pmic_reg_read(dev->parent, desc->vsel_reg); in pfuze100_regulator_val()
464 val &= desc->vsel_mask; in pfuze100_regulator_val()
465 *uV = desc->volt_table[val]; in pfuze100_regulator_val()
467 if (uc_pdata->min_uV < 0) { in pfuze100_regulator_val()
469 return -EINVAL; in pfuze100_regulator_val()
471 val = pmic_reg_read(dev->parent, desc->vsel_reg); in pfuze100_regulator_val()
474 val &= desc->vsel_mask; in pfuze100_regulator_val()
475 *uV = uc_pdata->min_uV + (int)val * desc->uV_step; in pfuze100_regulator_val()
481 if (uc_pdata->type == REGULATOR_TYPE_FIXED) { in pfuze100_regulator_val()
483 return -EINVAL; in pfuze100_regulator_val()
484 } else if (desc->volt_table) { in pfuze100_regulator_val()
485 for (i = 0; i < desc->vsel_mask; i++) { in pfuze100_regulator_val()
486 if (*uV == desc->volt_table[i]) in pfuze100_regulator_val()
489 if (i == desc->vsel_mask) { in pfuze100_regulator_val()
491 return -EINVAL; in pfuze100_regulator_val()
494 return pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_val()
495 desc->vsel_mask, i); in pfuze100_regulator_val()
497 if (uc_pdata->min_uV < 0) { in pfuze100_regulator_val()
499 return -EINVAL; in pfuze100_regulator_val()
501 return pmic_clrsetbits(dev->parent, desc->vsel_reg, in pfuze100_regulator_val()
502 desc->vsel_mask, in pfuze100_regulator_val()
503 (*uV - uc_pdata->min_uV) / desc->uV_step); in pfuze100_regulator_val()