Lines Matching +full:stm32f429 +full:- +full:pinctrl
3 #include <dm/pinctrl.h>
44 struct stm32_gpio_regs *regs = priv->regs; in stm32_pinctrl_get_af()
49 af = (readl(®s->afr[alt_index]) & in stm32_pinctrl_get_af()
64 * parse pin-controller sub-nodes (ie gpio bank nodes) and fill in stm32_populate_gpio_dev_list()
66 * current pin-controller. This list is used to find pin_name and in stm32_populate_gpio_dev_list()
69 list_for_each_entry(child, &dev->child_head, sibling_node) { in stm32_populate_gpio_dev_list()
70 ret = uclass_get_device_by_name(UCLASS_GPIO, child->name, in stm32_populate_gpio_dev_list()
78 return -ENOMEM; in stm32_populate_gpio_dev_list()
81 gpio_bank->gpio_dev = gpio_dev; in stm32_populate_gpio_dev_list()
82 list_add_tail(&gpio_bank->list, &priv->gpio_dev); in stm32_populate_gpio_dev_list()
96 * pin-controller, no need to run it again in stm32_pinctrl_get_pins_count()
98 if (priv->pinctrl_ngpios) in stm32_pinctrl_get_pins_count()
99 return priv->pinctrl_ngpios; in stm32_pinctrl_get_pins_count()
101 if (list_empty(&priv->gpio_dev)) in stm32_pinctrl_get_pins_count()
104 * walk through all banks to retrieve the pin-controller in stm32_pinctrl_get_pins_count()
107 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) { in stm32_pinctrl_get_pins_count()
108 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev); in stm32_pinctrl_get_pins_count()
110 priv->pinctrl_ngpios += uc_priv->gpio_count; in stm32_pinctrl_get_pins_count()
113 return priv->pinctrl_ngpios; in stm32_pinctrl_get_pins_count()
125 if (list_empty(&priv->gpio_dev)) in stm32_pinctrl_get_gpio_dev()
129 list_for_each_entry(gpio_bank, &priv->gpio_dev, list) { in stm32_pinctrl_get_gpio_dev()
130 uc_priv = dev_get_uclass_priv(gpio_bank->gpio_dev); in stm32_pinctrl_get_gpio_dev()
132 if (selector < (pin_count + uc_priv->gpio_count)) { in stm32_pinctrl_get_gpio_dev()
137 *idx = stm32_offset_to_index(gpio_bank->gpio_dev, in stm32_pinctrl_get_gpio_dev()
138 selector - pin_count); in stm32_pinctrl_get_gpio_dev()
142 return gpio_bank->gpio_dev; in stm32_pinctrl_get_gpio_dev()
144 pin_count += uc_priv->gpio_count; in stm32_pinctrl_get_gpio_dev()
165 uc_priv->bank_name, in stm32_pinctrl_get_pin_name()
187 return -ENODEV; in stm32_pinctrl_get_pin_muxing()
198 return -EINVAL; in stm32_pinctrl_get_pin_muxing()
223 INIT_LIST_HEAD(&priv->gpio_dev); in stm32_pinctrl_probe()
226 ret = hwspinlock_get_by_index(dev, 0, &priv->hws); in stm32_pinctrl_probe()
237 struct stm32_gpio_priv *priv = dev_get_priv(desc->dev); in stm32_gpio_config()
238 struct stm32_gpio_regs *regs = priv->regs; in stm32_gpio_config()
243 if (!ctl || ctl->af > 15 || ctl->mode > 3 || ctl->otype > 1 || in stm32_gpio_config()
244 ctl->pupd > 2 || ctl->speed > 3) in stm32_gpio_config()
245 return -EINVAL; in stm32_gpio_config()
247 ctrl_priv = dev_get_priv(dev_get_parent(desc->dev)); in stm32_gpio_config()
248 ret = hwspinlock_lock_timeout(&ctrl_priv->hws, 10); in stm32_gpio_config()
249 if (ret == -ETIME) { in stm32_gpio_config()
250 dev_err(desc->dev, "HWSpinlock timeout\n"); in stm32_gpio_config()
254 index = (desc->offset & 0x07) * 4; in stm32_gpio_config()
255 clrsetbits_le32(®s->afr[desc->offset >> 3], AFR_MASK << index, in stm32_gpio_config()
256 ctl->af << index); in stm32_gpio_config()
258 index = desc->offset * 2; in stm32_gpio_config()
259 clrsetbits_le32(®s->moder, MODE_BITS_MASK << index, in stm32_gpio_config()
260 ctl->mode << index); in stm32_gpio_config()
261 clrsetbits_le32(®s->ospeedr, OSPEED_MASK << index, in stm32_gpio_config()
262 ctl->speed << index); in stm32_gpio_config()
263 clrsetbits_le32(®s->pupdr, PUPD_MASK << index, ctl->pupd << index); in stm32_gpio_config()
265 index = desc->offset; in stm32_gpio_config()
266 clrsetbits_le32(®s->otyper, OTYPE_MSK << index, ctl->otype << index); in stm32_gpio_config()
268 hwspinlock_unlock(&ctrl_priv->hws); in stm32_gpio_config()
275 gpio_dsc->port = (port_pin & 0x1F000) >> 12; in prep_gpio_dsc()
276 gpio_dsc->pin = (port_pin & 0x0F00) >> 8; in prep_gpio_dsc()
277 debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port, in prep_gpio_dsc()
278 gpio_dsc->pin); in prep_gpio_dsc()
286 gpio_ctl->af = 0; in prep_gpio_ctl()
290 gpio_ctl->mode = STM32_GPIO_MODE_IN; in prep_gpio_ctl()
293 gpio_ctl->mode = STM32_GPIO_MODE_AF; in prep_gpio_ctl()
294 gpio_ctl->af = gpio_fn - 1; in prep_gpio_ctl()
297 gpio_ctl->mode = STM32_GPIO_MODE_AN; in prep_gpio_ctl()
300 gpio_ctl->mode = STM32_GPIO_MODE_OUT; in prep_gpio_ctl()
304 gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0); in prep_gpio_ctl()
306 if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain")) in prep_gpio_ctl()
307 gpio_ctl->otype = STM32_GPIO_OTYPE_OD; in prep_gpio_ctl()
309 gpio_ctl->otype = STM32_GPIO_OTYPE_PP; in prep_gpio_ctl()
311 if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up")) in prep_gpio_ctl()
312 gpio_ctl->pupd = STM32_GPIO_PUPD_UP; in prep_gpio_ctl()
313 else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down")) in prep_gpio_ctl()
314 gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN; in prep_gpio_ctl()
316 gpio_ctl->pupd = STM32_GPIO_PUPD_NO; in prep_gpio_ctl()
318 debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n", in prep_gpio_ctl()
319 __func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype, in prep_gpio_ctl()
320 gpio_ctl->pupd); in prep_gpio_ctl()
332 * usart1) of pin controller phandle "pinctrl-0" in stm32_pinctrl_config()
334 fdt_for_each_subnode(offset, gd->fdt_blob, offset) { in stm32_pinctrl_config()
339 len = fdtdec_get_int_array_count(gd->fdt_blob, offset, in stm32_pinctrl_config()
344 return -EINVAL; in stm32_pinctrl_config()
376 const void *fdt = gd->fdt_blob; in stm32_pinctrl_set_state_simple()
382 list = fdt_getprop(fdt, dev_of_offset(periph), "pinctrl-0", &size); in stm32_pinctrl_set_state_simple()
384 return -EINVAL; in stm32_pinctrl_set_state_simple()
386 debug("%s: periph->name = %s\n", __func__, periph->name); in stm32_pinctrl_set_state_simple()
394 pr_err("prop pinctrl-0 index %d invalid phandle\n", i); in stm32_pinctrl_set_state_simple()
395 return -EINVAL; in stm32_pinctrl_set_state_simple()
421 { .compatible = "st,stm32f429-pinctrl" },
422 { .compatible = "st,stm32f469-pinctrl" },
423 { .compatible = "st,stm32f746-pinctrl" },
424 { .compatible = "st,stm32h743-pinctrl" },
425 { .compatible = "st,stm32mp157-pinctrl" },
426 { .compatible = "st,stm32mp157-z-pinctrl" },