1 // SPDX-License-Identifier: GPL-2.0
9 #include <dm/device-internal.h>
13 #include <asm-generic/gpio.h>
15 #include "pinctrl-mtk-common.h"
18  * struct mtk_drive_desc - the structure that holds the information
25  * formula: output = ((input) / step - 1) * scal
49 	__raw_writel(val, priv->base + reg);  in mtk_w32()
56 	return __raw_readl(priv->base + reg);  in mtk_r32()
63 	order = fls(count) - 1;  in get_count_order()
64 	if (count & (count - 1))  in get_count_order()
86 	c = rc->range;  in mtk_hw_pin_field_lookup()
87 	e = c + rc->nranges;  in mtk_hw_pin_field_lookup()
90 		if (pin >= c->s_pin && pin <= c->e_pin)  in mtk_hw_pin_field_lookup()
96 		return -EINVAL;  in mtk_hw_pin_field_lookup()
99 	 * if c->fixed is held, that determines the all the pins in the  in mtk_hw_pin_field_lookup()
102 	bits = c->fixed ? c->s_bit : c->s_bit + (pin - c->s_pin) * (c->x_bits);  in mtk_hw_pin_field_lookup()
104 	/* Fill pfd from bits. For example 32-bit register applied is assumed  in mtk_hw_pin_field_lookup()
105 	 * when c->sz_reg is equal to 32.  in mtk_hw_pin_field_lookup()
107 	pfd->offset = c->s_addr + c->x_addrs * (bits / c->sz_reg);  in mtk_hw_pin_field_lookup()
108 	pfd->bitpos = bits % c->sz_reg;  in mtk_hw_pin_field_lookup()
109 	pfd->mask = (1 << c->x_bits) - 1;  in mtk_hw_pin_field_lookup()
111 	/* pfd->next is used for indicating that bit wrapping-around happens  in mtk_hw_pin_field_lookup()
115 	pfd->next = pfd->bitpos + c->x_bits > c->sz_reg ? c->x_addrs : 0;  in mtk_hw_pin_field_lookup()
127 		return -EINVAL;  in mtk_hw_pin_field_get()
129 	if (priv->soc->reg_cal && priv->soc->reg_cal[field].range)  in mtk_hw_pin_field_get()
130 		rc = &priv->soc->reg_cal[field];  in mtk_hw_pin_field_get()
132 		return -EINVAL;  in mtk_hw_pin_field_get()
139 	*l = 32 - pf->bitpos;  in mtk_hw_bits_part()
140 	*h = get_count_order(pf->mask) - *l;  in mtk_hw_bits_part()
150 	mtk_rmw(dev, pf->offset, pf->mask << pf->bitpos,  in mtk_hw_write_cross_field()
151 		(value & pf->mask) << pf->bitpos);  in mtk_hw_write_cross_field()
153 	mtk_rmw(dev, pf->offset + pf->next, BIT(nbits_h) - 1,  in mtk_hw_write_cross_field()
154 		(value & pf->mask) >> nbits_l);  in mtk_hw_write_cross_field()
164 	l  = (mtk_r32(dev, pf->offset) >> pf->bitpos) & (BIT(nbits_l) - 1);  in mtk_hw_read_cross_field()
165 	h  = (mtk_r32(dev, pf->offset + pf->next)) & (BIT(nbits_h) - 1);  in mtk_hw_read_cross_field()
211 	return priv->soc->ngrps;  in mtk_get_groups_count()
219 	if (!priv->soc->grps[selector].name)  in mtk_get_pin_name()
222 	return priv->soc->pins[selector].name;  in mtk_get_pin_name()
229 	return priv->soc->npins;  in mtk_get_pins_count()
237 	if (!priv->soc->grps[selector].name)  in mtk_get_group_name()
240 	return priv->soc->grps[selector].name;  in mtk_get_group_name()
247 	return priv->soc->nfuncs;  in mtk_get_functions_count()
255 	if (!priv->soc->funcs[selector].name)  in mtk_get_function_name()
258 	return priv->soc->funcs[selector].name;  in mtk_get_function_name()
267 			&priv->soc->grps[group_selector];  in mtk_pinmux_group_set()
270 	for (i = 0; i < grp->num_pins; i++) {  in mtk_pinmux_group_set()
271 		int *pin_modes = grp->data;  in mtk_pinmux_group_set()
273 		mtk_hw_set_value(dev, grp->pins[i], PINCTRL_PIN_REG_MODE,  in mtk_pinmux_group_set()
280 #if CONFIG_IS_ENABLED(PINCONF)
282 	{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
283 	{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
284 	{ "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
285 	{ "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
286 	{ "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
287 	{ "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
288 	{ "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
289 	{ "output-enable", PIN_CONFIG_OUTPUT_ENABLE, 1 },
290 	{ "output-high", PIN_CONFIG_OUTPUT, 1, },
291 	{ "output-low", PIN_CONFIG_OUTPUT, 0, },
292 	{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
298 	const struct mtk_pin_desc *desc = &priv->soc->pins[pin];  in mtk_pinconf_drive_set()
300 	int err = -ENOTSUPP;  in mtk_pinconf_drive_set()
302 	tb = &mtk_drive[desc->drv_n];  in mtk_pinconf_drive_set()
308 	if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {  in mtk_pinconf_drive_set()
309 		arg = (arg / tb->step - 1) * tb->scal;  in mtk_pinconf_drive_set()
388 		err = -ENOTSUPP;  in mtk_pinconf_set()
402 			&priv->soc->grps[group_selector];  in mtk_pinconf_group_set()
405 	for (i = 0; i < grp->num_pins; i++) {  in mtk_pinconf_group_set()
406 		ret = mtk_pinconf_set(dev, grp->pins[i], param, arg);  in mtk_pinconf_group_set()
423 #if CONFIG_IS_ENABLED(PINCONF)
436 	err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DI, &val);  in mtk_gpio_get()
445 	return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DO, !!val);  in mtk_gpio_set()
452 	err = mtk_hw_get_value(dev->parent, off, PINCTRL_PIN_REG_DIR, &val);  in mtk_gpio_get_direction()
461 	return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 0);  in mtk_gpio_direction_input()
470 	return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_DIR, 1);  in mtk_gpio_direction_output()
476 	return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE, 0);  in mtk_gpio_request()
481 	struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent);  in mtk_gpio_probe()
485 	uc_priv->bank_name = priv->soc->name;  in mtk_gpio_probe()
486 	uc_priv->gpio_count = priv->soc->npins;  in mtk_gpio_probe()
509 	struct uclass_driver *drv;  in mtk_gpiochip_register()  local
514 	drv = lists_uclass_lookup(UCLASS_GPIO);  in mtk_gpiochip_register()
515 	if (!drv)  in mtk_gpiochip_register()
516 		return -ENOENT;  in mtk_gpiochip_register()
519 		if (ofnode_read_bool(node, "gpio-controller")) {  in mtk_gpiochip_register()
542 	priv->base = dev_read_addr_ptr(dev);  in mtk_pinctrl_common_probe()
543 	if (priv->base == (void *)FDT_ADDR_T_NONE)  in mtk_pinctrl_common_probe()
544 		return -EINVAL;  in mtk_pinctrl_common_probe()
546 	priv->soc = soc;  in mtk_pinctrl_common_probe()