109 	u32 val;  in omap_pipe3_wait_lock()  local
114 		val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);  in omap_pipe3_wait_lock()
115 		if (val & PLL_LOCK)  in omap_pipe3_wait_lock()
119 	if (!(val & PLL_LOCK)) {  in omap_pipe3_wait_lock()
129 	u32                     val;  in omap_pipe3_dpll_program()  local
138 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);  in omap_pipe3_dpll_program()
139 	val &= ~PLL_REGN_MASK;  in omap_pipe3_dpll_program()
140 	val |= dpll_params->n << PLL_REGN_SHIFT;  in omap_pipe3_dpll_program()
141 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);  in omap_pipe3_dpll_program()
143 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);  in omap_pipe3_dpll_program()
144 	val &= ~(PLL_SELFREQDCO_MASK | PLL_IDLE);  in omap_pipe3_dpll_program()
145 	val |= dpll_params->freq << PLL_SELFREQDCO_SHIFT;  in omap_pipe3_dpll_program()
146 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);  in omap_pipe3_dpll_program()
148 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION1);  in omap_pipe3_dpll_program()
149 	val &= ~PLL_REGM_MASK;  in omap_pipe3_dpll_program()
150 	val |= dpll_params->m << PLL_REGM_SHIFT;  in omap_pipe3_dpll_program()
151 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION1, val);  in omap_pipe3_dpll_program()
153 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION4);  in omap_pipe3_dpll_program()
154 	val &= ~PLL_REGM_F_MASK;  in omap_pipe3_dpll_program()
155 	val |= dpll_params->mf << PLL_REGM_F_SHIFT;  in omap_pipe3_dpll_program()
156 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION4, val);  in omap_pipe3_dpll_program()
158 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION3);  in omap_pipe3_dpll_program()
159 	val &= ~PLL_SD_MASK;  in omap_pipe3_dpll_program()
160 	val |= dpll_params->sd << PLL_SD_SHIFT;  in omap_pipe3_dpll_program()
161 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION3, val);  in omap_pipe3_dpll_program()
170 	u32 val, rate;  in omap_control_pipe3_power()  local
172 	val = readl(pipe3->power_reg);  in omap_control_pipe3_power()
178 		val &= ~(OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK |  in omap_control_pipe3_power()
180 		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON <<  in omap_control_pipe3_power()
182 		val |= rate <<  in omap_control_pipe3_power()
185 		val &= ~OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK;  in omap_control_pipe3_power()
186 		val |= OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF <<  in omap_control_pipe3_power()
190 	writel(val, pipe3->power_reg);  in omap_control_pipe3_power()
196 	u32 val;  in pipe3_init()  local
200 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);  in pipe3_init()
201 	if (!(val & PLL_LOCK)) {  in pipe3_init()
207 		val = omap_pipe3_readl(pipe3->pll_ctrl_base,  in pipe3_init()
209 		if (val & PLL_IDLE) {  in pipe3_init()
210 			val &= ~PLL_IDLE;  in pipe3_init()
212 					  PLL_CONFIGURATION2, val);  in pipe3_init()
243 	u32 val;  in pipe3_exit()  local
250 	val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_CONFIGURATION2);  in pipe3_exit()
251 	val |= PLL_IDLE;  in pipe3_exit()
252 	omap_pipe3_writel(pipe3->pll_ctrl_base, PLL_CONFIGURATION2, val);  in pipe3_exit()
257 		val = omap_pipe3_readl(pipe3->pll_ctrl_base, PLL_STATUS);  in pipe3_exit()
258 		if ((val & PLL_TICOPWDN) && (val & PLL_LDOPWDN))  in pipe3_exit()
262 	if (!(val & PLL_TICOPWDN) || !(val & PLL_LDOPWDN)) {  in pipe3_exit()
264 		      __func__, val);  in pipe3_exit()
269 		val = readl(pipe3->pll_reset_reg);  in pipe3_exit()
270 		writel(val | SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);  in pipe3_exit()
272 		writel(val & ~SATA_PLL_SOFT_RESET, pipe3->pll_reset_reg);  in pipe3_exit()