Lines Matching +full:mux +full:- +full:add +full:- +full:data
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Marvell International Ltd.
31 * For CP-110 we have 2 Selector registers "PHY Selectors",
73 u32 data; in polling_with_timeout() local
77 data = readl(addr) & mask; in polling_with_timeout()
78 } while (data != val && --usec_timout > 0); in polling_with_timeout()
81 return data; in polling_with_timeout()
90 u32 mask, data, ret = 1; in comphy_pcie_power_up() local
100 * Add SAR (Sample-At-Reset) configuration for the PCIe clock in comphy_pcie_power_up()
102 * U-Boot to mainline version. in comphy_pcie_power_up()
104 * SerDes Lane 4/5 got the PCIe ref-clock #1, in comphy_pcie_power_up()
105 * and SerDes Lane 0 got PCIe ref-clock #0 in comphy_pcie_power_up()
126 * we need to configure the clock-source MUX. in comphy_pcie_power_up()
135 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_pcie_power_up()
136 /* RFU configurations - hard reset comphy */ in comphy_pcie_power_up()
138 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_pcie_power_up()
140 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_pcie_power_up()
142 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in comphy_pcie_power_up()
144 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_pcie_power_up()
146 data |= 0x0 << COMMON_PHY_PHY_MODE_OFFSET; in comphy_pcie_power_up()
147 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
151 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in comphy_pcie_power_up()
153 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_pcie_power_up()
154 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
156 /* Wait 1ms - until band gap and ref clock ready */ in comphy_pcie_power_up()
162 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; in comphy_pcie_power_up()
165 data |= 0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; in comphy_pcie_power_up()
166 /* Set Data bus width USB mode for V0 */ in comphy_pcie_power_up()
168 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; in comphy_pcie_power_up()
171 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; in comphy_pcie_power_up()
172 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in comphy_pcie_power_up()
174 data = 0x2 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET; in comphy_pcie_power_up()
177 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET; in comphy_pcie_power_up()
179 data |= 0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET; in comphy_pcie_power_up()
182 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); in comphy_pcie_power_up()
184 /* Set PIPE mode interface to PCIe3 - 0x1 & set lane order */ in comphy_pcie_power_up()
185 data = 0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET; in comphy_pcie_power_up()
192 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET; in comphy_pcie_power_up()
193 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET; in comphy_pcie_power_up()
194 } else if (lane == (pcie_width - 1)) { in comphy_pcie_power_up()
195 data |= 0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET; in comphy_pcie_power_up()
198 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); in comphy_pcie_power_up()
207 /* TODO: check if pcie clock is output/input - for bringup use input*/ in comphy_pcie_power_up()
210 data = 0; in comphy_pcie_power_up()
211 /* Only if clock is output, configure the clock-source mux */ in comphy_pcie_power_up()
214 data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; in comphy_pcie_power_up()
221 data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; in comphy_pcie_power_up()
224 data |= 0x1 << HPIPE_MISC_CLK500_EN_OFFSET; in comphy_pcie_power_up()
228 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; in comphy_pcie_power_up()
232 data |= 0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET; in comphy_pcie_power_up()
235 data |= 0x1 << HPIPE_MISC_ICP_FORCE_OFFSET; in comphy_pcie_power_up()
236 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in comphy_pcie_power_up()
238 /* Set reference frequcency select - 0x2 for 25MHz*/ in comphy_pcie_power_up()
240 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_pcie_power_up()
242 /* Set reference frequcency select - 0x0 for 100MHz*/ in comphy_pcie_power_up()
244 data = 0x0 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_pcie_power_up()
248 data |= 0x3 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_pcie_power_up()
249 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_pcie_power_up()
254 data = 0x0 << HPIPE_LANE_ALIGN_OFF_OFFSET; in comphy_pcie_power_up()
255 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); in comphy_pcie_power_up()
259 * Set the amount of time spent in the LoZ state - set for 0x7 only if in comphy_pcie_power_up()
270 data = 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET; in comphy_pcie_power_up()
271 /* Bypass frame detection and sync detection for RX DATA */ in comphy_pcie_power_up()
273 data = 0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET; in comphy_pcie_power_up()
276 data |= 0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET; in comphy_pcie_power_up()
277 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); in comphy_pcie_power_up()
281 data = 0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET; in comphy_pcie_power_up()
284 data |= 0x2 << HPIPE_PCIE_SEL_BITS_OFFSET; in comphy_pcie_power_up()
285 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); in comphy_pcie_power_up()
289 data = 0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET; in comphy_pcie_power_up()
292 data |= 0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET; in comphy_pcie_power_up()
295 data |= 0x0 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET; in comphy_pcie_power_up()
296 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in comphy_pcie_power_up()
300 data = 0x0 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET; in comphy_pcie_power_up()
303 data |= 0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET; in comphy_pcie_power_up()
304 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in comphy_pcie_power_up()
309 data = 0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET; in comphy_pcie_power_up()
312 data |= 0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET; in comphy_pcie_power_up()
315 data |= 0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET; in comphy_pcie_power_up()
316 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); in comphy_pcie_power_up()
320 data = 0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET; in comphy_pcie_power_up()
323 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET; in comphy_pcie_power_up()
326 data |= 0x0 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET; in comphy_pcie_power_up()
329 data |= 0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET; in comphy_pcie_power_up()
330 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in comphy_pcie_power_up()
334 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; in comphy_pcie_power_up()
335 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in comphy_pcie_power_up()
339 data = 0x17 << HPIPE_TRX_TRAIN_TIMER_OFFSET; in comphy_pcie_power_up()
340 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); in comphy_pcie_power_up()
345 data = 0; in comphy_pcie_power_up()
346 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in comphy_pcie_power_up()
350 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in comphy_pcie_power_up()
351 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_pcie_power_up()
355 data = 0x3 << HPIPE_G3_DFE_RES_OFFSET; in comphy_pcie_power_up()
356 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in comphy_pcie_power_up()
360 data = 0x0 << HPIPE_DFE_RES_FORCE_OFFSET; in comphy_pcie_power_up()
361 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in comphy_pcie_power_up()
365 data = 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; in comphy_pcie_power_up()
368 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; in comphy_pcie_power_up()
371 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; in comphy_pcie_power_up()
372 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in comphy_pcie_power_up()
376 data = 0x1 << HPIPE_SMAPLER_OFFSET; in comphy_pcie_power_up()
377 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_pcie_power_up()
383 data = 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; in comphy_pcie_power_up()
386 data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; in comphy_pcie_power_up()
387 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in comphy_pcie_power_up()
391 data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; in comphy_pcie_power_up()
392 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in comphy_pcie_power_up()
396 data = 0x1 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET; in comphy_pcie_power_up()
398 data |= 0x0 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET; in comphy_pcie_power_up()
400 data |= 0x0 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET; in comphy_pcie_power_up()
401 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); in comphy_pcie_power_up()
403 data = 0x0 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET; in comphy_pcie_power_up()
404 reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask); in comphy_pcie_power_up()
408 data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; in comphy_pcie_power_up()
410 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; in comphy_pcie_power_up()
412 data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; in comphy_pcie_power_up()
413 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in comphy_pcie_power_up()
417 data = 0x3 << HPIPE_G2_DFE_RES_OFFSET; in comphy_pcie_power_up()
418 reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask); in comphy_pcie_power_up()
422 data = 0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET; in comphy_pcie_power_up()
423 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in comphy_pcie_power_up()
427 data = 0x16 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; in comphy_pcie_power_up()
428 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in comphy_pcie_power_up()
430 /* Set PLL Charge-pump Current Control */ in comphy_pcie_power_up()
432 data = 0x4 << HPIPE_G3_SETTING_5_G3_ICP_OFFSET; in comphy_pcie_power_up()
433 reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask); in comphy_pcie_power_up()
437 data = 0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET; in comphy_pcie_power_up()
439 data |= 0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET; in comphy_pcie_power_up()
441 data |= 0x2 << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET; in comphy_pcie_power_up()
442 reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask); in comphy_pcie_power_up()
447 data = 0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET; in comphy_pcie_power_up()
448 reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask); in comphy_pcie_power_up()
454 * For PCIe by4 or by2 - release from reset only after finish to in comphy_pcie_power_up()
457 if ((pcie_width == 1) || (lane == (pcie_width - 1))) { in comphy_pcie_power_up()
471 * for PCIe by4 or by2 - release from soft reset in comphy_pcie_power_up()
472 * all lanes - can't use read modify write in comphy_pcie_power_up()
482 * for PCIe by4 or by2 - release from soft reset in comphy_pcie_power_up()
504 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; in comphy_pcie_power_up()
505 mask = data; in comphy_pcie_power_up()
506 data = polling_with_timeout(addr, data, mask, 15000); in comphy_pcie_power_up()
507 if (data != 0) { in comphy_pcie_power_up()
508 debug("Read from reg = %p - value = 0x%x\n", in comphy_pcie_power_up()
510 data); in comphy_pcie_power_up()
524 u32 mask, data, ret = 1; in comphy_usb3_power_up() local
530 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_usb3_power_up()
531 /* RFU configurations - hard reset comphy */ in comphy_usb3_power_up()
533 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_usb3_power_up()
535 data |= 0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_usb3_power_up()
537 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in comphy_usb3_power_up()
539 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_usb3_power_up()
541 data |= 0x1 << COMMON_PHY_PHY_MODE_OFFSET; in comphy_usb3_power_up()
542 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_usb3_power_up()
546 data = 0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in comphy_usb3_power_up()
548 data |= 0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_usb3_power_up()
549 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_usb3_power_up()
551 /* Wait 1ms - until band gap and ref clock ready */ in comphy_usb3_power_up()
558 data = 0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET; in comphy_usb3_power_up()
561 data |= 0x0 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET; in comphy_usb3_power_up()
562 /* Set Data bus width USB mode for V0 */ in comphy_usb3_power_up()
564 data |= 0x0 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET; in comphy_usb3_power_up()
567 data |= 0x0 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET; in comphy_usb3_power_up()
568 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in comphy_usb3_power_up()
573 /* Set reference clock to come from group 1 - 25Mhz */ in comphy_usb3_power_up()
577 /* Set reference frequcency select - 0x2 */ in comphy_usb3_power_up()
579 data = 0x2 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_usb3_power_up()
580 /* Set PHY mode to USB - 0x5 */ in comphy_usb3_power_up()
582 data |= 0x5 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_usb3_power_up()
583 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_usb3_power_up()
584 /* Set the amount of time spent in the LoZ state - set for 0x7 */ in comphy_usb3_power_up()
588 /* Set max PHY generation setting - 5Gbps */ in comphy_usb3_power_up()
592 /* Set select data width 20Bit (SEL_BITS[2:0]) */ in comphy_usb3_power_up()
596 /* select de-emphasize 3.5db */ in comphy_usb3_power_up()
607 /* Set Pin DFE_PAT_DIS -> Bit[1]: PIN_DFE_PAT_DIS = 0x0 */ in comphy_usb3_power_up()
609 data = 0x1 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET; in comphy_usb3_power_up()
612 data |= 0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET; in comphy_usb3_power_up()
615 data |= 0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET; in comphy_usb3_power_up()
616 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in comphy_usb3_power_up()
625 /* wait 15ms - for comphy calibration done */ in comphy_usb3_power_up()
629 data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; in comphy_usb3_power_up()
630 mask = data; in comphy_usb3_power_up()
631 data = polling_with_timeout(addr, data, mask, 15000); in comphy_usb3_power_up()
632 if (data != 0) { in comphy_usb3_power_up()
633 debug("Read from reg = %p - value = 0x%x\n", in comphy_usb3_power_up()
634 hpipe_addr + HPIPE_LANE_STATUS1_REG, data); in comphy_usb3_power_up()
647 u32 mask, data, i, ret = 1; in comphy_sata_power_up() local
653 int sata_node = -1; /* Set to -1 in order to read the first sata node */ in comphy_sata_power_up()
658 * Assumption - each CP has only one SATA controller in comphy_sata_power_up()
659 * Calling fdt_node_offset_by_compatible first time (with sata_node = -1 in comphy_sata_power_up()
666 gd->fdt_blob, sata_node, "marvell,armada-8k-ahci"); in comphy_sata_power_up()
674 gd->fdt_blob, sata_node, "reg", 0, NULL, true); in comphy_sata_power_up()
682 debug("stage: MAC configuration - power down comphy\n"); in comphy_sata_power_up()
692 data = 0x1 << SATA3_CTRL_SATA0_PD_OFFSET; in comphy_sata_power_up()
695 data |= 0x1 << SATA3_CTRL_SATA1_PD_OFFSET; in comphy_sata_power_up()
698 data |= 0x0 << SATA3_CTRL_SATA1_ENABLE_OFFSET; in comphy_sata_power_up()
701 data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET; in comphy_sata_power_up()
702 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); in comphy_sata_power_up()
704 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_sata_power_up()
705 /* RFU configurations - hard reset comphy */ in comphy_sata_power_up()
707 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_sata_power_up()
709 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_sata_power_up()
711 data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET; in comphy_sata_power_up()
713 data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET; in comphy_sata_power_up()
714 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_sata_power_up()
716 /* Set select data width 40Bit - SATA mode only */ in comphy_sata_power_up()
723 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_sata_power_up()
725 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_sata_power_up()
726 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sata_power_up()
728 /* Wait 1ms - until band gap and ref clock ready */ in comphy_sata_power_up()
733 /* Set reference clock to comes from group 1 - choose 25Mhz */ in comphy_sata_power_up()
739 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_sata_power_up()
742 data |= 0x0 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_sata_power_up()
743 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_sata_power_up()
744 /* Set max PHY generation setting - 6Gbps */ in comphy_sata_power_up()
748 /* Set select data width 40Bit (SEL_BITS[2:0]) */ in comphy_sata_power_up()
756 data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; in comphy_sata_power_up()
758 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; in comphy_sata_power_up()
760 data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; in comphy_sata_power_up()
762 data |= 0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; in comphy_sata_power_up()
764 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; in comphy_sata_power_up()
765 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in comphy_sata_power_up()
768 data = 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; in comphy_sata_power_up()
770 data |= 0x2 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; in comphy_sata_power_up()
772 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; in comphy_sata_power_up()
774 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET; in comphy_sata_power_up()
776 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET; in comphy_sata_power_up()
777 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in comphy_sata_power_up()
781 data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; in comphy_sata_power_up()
783 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; in comphy_sata_power_up()
785 data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; in comphy_sata_power_up()
787 data |= 0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET; in comphy_sata_power_up()
789 data |= 0x1 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET; in comphy_sata_power_up()
790 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in comphy_sata_power_up()
794 data = 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET; in comphy_sata_power_up()
796 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET; in comphy_sata_power_up()
798 data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET; in comphy_sata_power_up()
800 data |= 0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET; in comphy_sata_power_up()
802 data |= 0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET; in comphy_sata_power_up()
804 data |= 0x2 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET; in comphy_sata_power_up()
806 data |= 0x0 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET; in comphy_sata_power_up()
807 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in comphy_sata_power_up()
811 data = 0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET; in comphy_sata_power_up()
813 data |= 0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET; in comphy_sata_power_up()
815 data |= 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in comphy_sata_power_up()
817 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET; in comphy_sata_power_up()
819 data |= 0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET; in comphy_sata_power_up()
821 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET; in comphy_sata_power_up()
823 data |= 0x1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET; in comphy_sata_power_up()
824 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_sata_power_up()
828 data = 0x1 << HPIPE_SMAPLER_OFFSET; in comphy_sata_power_up()
829 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sata_power_up()
831 data = 0x0 << HPIPE_SMAPLER_OFFSET; in comphy_sata_power_up()
832 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sata_power_up()
836 data = 0x10 << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; in comphy_sata_power_up()
837 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in comphy_sata_power_up()
841 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; in comphy_sata_power_up()
842 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in comphy_sata_power_up()
844 /* DFE F3-F5 Coefficient Control */ in comphy_sata_power_up()
846 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; in comphy_sata_power_up()
848 data = 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; in comphy_sata_power_up()
849 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in comphy_sata_power_up()
853 data = 0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET; in comphy_sata_power_up()
855 data |= 0x4 << HPIPE_G3_FFE_RES_SEL_OFFSET; in comphy_sata_power_up()
857 data |= 0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET; in comphy_sata_power_up()
859 data |= 0x1 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET; in comphy_sata_power_up()
861 data |= 0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET; in comphy_sata_power_up()
862 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in comphy_sata_power_up()
866 data = 0x2 << HPIPE_G3_DFE_RES_OFFSET; in comphy_sata_power_up()
867 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in comphy_sata_power_up()
871 data = 0x5c << HPIPE_OS_PH_OFFSET_OFFSET; in comphy_sata_power_up()
873 data |= 0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET; in comphy_sata_power_up()
874 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in comphy_sata_power_up()
876 data = 0x1 << HPIPE_OS_PH_VALID_OFFSET; in comphy_sata_power_up()
877 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in comphy_sata_power_up()
879 data = 0x0 << HPIPE_OS_PH_VALID_OFFSET; in comphy_sata_power_up()
880 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in comphy_sata_power_up()
884 data = 0x8 << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; in comphy_sata_power_up()
886 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET; in comphy_sata_power_up()
888 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; in comphy_sata_power_up()
890 data |= 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET; in comphy_sata_power_up()
891 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in comphy_sata_power_up()
895 data = 0xa << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET; in comphy_sata_power_up()
897 data |= 0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET; in comphy_sata_power_up()
899 data |= 0x2 << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET; in comphy_sata_power_up()
901 data |= 0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET; in comphy_sata_power_up()
902 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); in comphy_sata_power_up()
906 data = 0xe << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET; in comphy_sata_power_up()
908 data |= 0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET; in comphy_sata_power_up()
910 data |= 0x6 << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET; in comphy_sata_power_up()
912 data |= 0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET; in comphy_sata_power_up()
914 data |= 0x4 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET; in comphy_sata_power_up()
916 data |= 0x0 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET; in comphy_sata_power_up()
917 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); in comphy_sata_power_up()
921 data = 0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET; in comphy_sata_power_up()
922 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in comphy_sata_power_up()
933 data = mask = 0; in comphy_sata_power_up()
935 data |= (1 << HPIPE_SYNC_PATTERN_TXD_SWAP_OFFSET); in comphy_sata_power_up()
939 data |= (1 << HPIPE_SYNC_PATTERN_RXD_SWAP_OFFSET); in comphy_sata_power_up()
942 reg_set(hpipe_addr + HPIPE_SYNC_PATTERN_REG, data, mask); in comphy_sata_power_up()
954 * MAC configuration power up comphy - power up PLL/TX/RX in comphy_sata_power_up()
962 data = 0x0 << SATA3_CTRL_SATA0_PD_OFFSET; in comphy_sata_power_up()
965 data |= 0x0 << SATA3_CTRL_SATA1_PD_OFFSET; in comphy_sata_power_up()
968 data |= 0x1 << SATA3_CTRL_SATA1_ENABLE_OFFSET; in comphy_sata_power_up()
971 data |= 0x1 << SATA3_CTRL_SATA_SSU_OFFSET; in comphy_sata_power_up()
972 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); in comphy_sata_power_up()
985 data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & in comphy_sata_power_up()
987 mask = data; in comphy_sata_power_up()
988 data = polling_with_timeout(addr, data, mask, 15000); in comphy_sata_power_up()
989 if (data != 0) { in comphy_sata_power_up()
990 debug("Read from reg = %p - value = 0x%x\n", in comphy_sata_power_up()
991 hpipe_addr + HPIPE_LANE_STATUS1_REG, data); in comphy_sata_power_up()
993 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK), in comphy_sata_power_up()
994 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK)); in comphy_sata_power_up()
1006 u32 mask, data, ret = 1; in comphy_sgmii_power_up() local
1013 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_sgmii_power_up()
1014 /* RFU configurations - hard reset comphy */ in comphy_sgmii_power_up()
1016 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_sgmii_power_up()
1018 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_sgmii_power_up()
1019 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_sgmii_power_up()
1023 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_sgmii_power_up()
1027 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in comphy_sgmii_power_up()
1028 data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in comphy_sgmii_power_up()
1031 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in comphy_sgmii_power_up()
1032 data |= 0x8 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in comphy_sgmii_power_up()
1035 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_sgmii_power_up()
1037 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_sgmii_power_up()
1039 data |= 1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; in comphy_sgmii_power_up()
1040 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sgmii_power_up()
1044 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_sgmii_power_up()
1046 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_sgmii_power_up()
1048 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_sgmii_power_up()
1049 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1053 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_sgmii_power_up()
1055 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_sgmii_power_up()
1056 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1059 /* Wait 1ms - until band gap and ref clock ready */ in comphy_sgmii_power_up()
1066 data = 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; in comphy_sgmii_power_up()
1067 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in comphy_sgmii_power_up()
1070 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_sgmii_power_up()
1072 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_sgmii_power_up()
1073 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_sgmii_power_up()
1076 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; in comphy_sgmii_power_up()
1077 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in comphy_sgmii_power_up()
1080 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; in comphy_sgmii_power_up()
1082 data |= 0x0 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; in comphy_sgmii_power_up()
1083 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in comphy_sgmii_power_up()
1086 data = 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in comphy_sgmii_power_up()
1087 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_sgmii_power_up()
1089 /* Set analog paramters from ETP(HW) - for now use the default datas */ in comphy_sgmii_power_up()
1096 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); in comphy_sgmii_power_up()
1099 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_sgmii_power_up()
1101 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_sgmii_power_up()
1103 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_sgmii_power_up()
1104 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sgmii_power_up()
1108 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | in comphy_sgmii_power_up()
1110 mask = data; in comphy_sgmii_power_up()
1111 data = polling_with_timeout(addr, data, mask, 15000); in comphy_sgmii_power_up()
1112 if (data != 0) { in comphy_sgmii_power_up()
1113 debug("Read from reg = %p - value = 0x%x\n", in comphy_sgmii_power_up()
1114 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sgmii_power_up()
1116 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), in comphy_sgmii_power_up()
1117 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); in comphy_sgmii_power_up()
1123 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in comphy_sgmii_power_up()
1124 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1128 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; in comphy_sgmii_power_up()
1129 mask = data; in comphy_sgmii_power_up()
1130 data = polling_with_timeout(addr, data, mask, 100); in comphy_sgmii_power_up()
1131 if (data != 0) { in comphy_sgmii_power_up()
1132 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sgmii_power_up()
1140 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in comphy_sgmii_power_up()
1142 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_sgmii_power_up()
1143 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1152 u32 mask, data, ret = 1; in comphy_sfi_power_up() local
1159 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_sfi_power_up()
1160 /* RFU configurations - hard reset comphy */ in comphy_sfi_power_up()
1162 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_sfi_power_up()
1164 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_sfi_power_up()
1165 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_sfi_power_up()
1169 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_sfi_power_up()
1171 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in comphy_sfi_power_up()
1173 data |= 0xE << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in comphy_sfi_power_up()
1175 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_sfi_power_up()
1177 data |= 0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_sfi_power_up()
1179 data |= 0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; in comphy_sfi_power_up()
1180 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sfi_power_up()
1184 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_sfi_power_up()
1186 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_sfi_power_up()
1188 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_sfi_power_up()
1189 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1192 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_sfi_power_up()
1194 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_sfi_power_up()
1195 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1198 /* Wait 1ms - until band gap and ref clock ready */ in comphy_sfi_power_up()
1205 data = (speed == PHY_SPEED_5_15625G) ? in comphy_sfi_power_up()
1209 data |= 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET; in comphy_sfi_power_up()
1210 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in comphy_sfi_power_up()
1213 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_sfi_power_up()
1215 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_sfi_power_up()
1216 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_sfi_power_up()
1219 data = 0x1 << HPIPE_LOOPBACK_SEL_OFFSET; in comphy_sfi_power_up()
1220 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in comphy_sfi_power_up()
1223 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; in comphy_sfi_power_up()
1225 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; in comphy_sfi_power_up()
1226 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in comphy_sfi_power_up()
1229 data = 0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET; in comphy_sfi_power_up()
1230 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_sfi_power_up()
1235 data = 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET; in comphy_sfi_power_up()
1237 data |= 1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET; in comphy_sfi_power_up()
1239 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET; in comphy_sfi_power_up()
1241 data |= 1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET; in comphy_sfi_power_up()
1244 data = 0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET; in comphy_sfi_power_up()
1246 reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); in comphy_sfi_power_up()
1252 data = 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET; in comphy_sfi_power_up()
1253 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in comphy_sfi_power_up()
1254 /* 0x7-DFE Resolution control */ in comphy_sfi_power_up()
1256 data = 0x1 << HPIPE_DFE_RES_FORCE_OFFSET; in comphy_sfi_power_up()
1257 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in comphy_sfi_power_up()
1258 /* 0xd-G1_Setting_0 */ in comphy_sfi_power_up()
1261 data = 0x6 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; in comphy_sfi_power_up()
1264 data = 0x1c << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET; in comphy_sfi_power_up()
1266 data |= 0xe << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET; in comphy_sfi_power_up()
1268 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in comphy_sfi_power_up()
1271 data = 0x0 << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET; in comphy_sfi_power_up()
1273 data |= 0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET; in comphy_sfi_power_up()
1274 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); in comphy_sfi_power_up()
1277 data = 0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET; in comphy_sfi_power_up()
1279 data |= 0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET; in comphy_sfi_power_up()
1280 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); in comphy_sfi_power_up()
1283 data = 0xe << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; in comphy_sfi_power_up()
1285 data |= 0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET; in comphy_sfi_power_up()
1286 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); in comphy_sfi_power_up()
1289 data = 0 << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET; in comphy_sfi_power_up()
1290 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); in comphy_sfi_power_up()
1291 /* 0xE-G1_Setting_1 */ in comphy_sfi_power_up()
1293 data = 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; in comphy_sfi_power_up()
1296 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; in comphy_sfi_power_up()
1298 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; in comphy_sfi_power_up()
1301 data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; in comphy_sfi_power_up()
1303 data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; in comphy_sfi_power_up()
1305 data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; in comphy_sfi_power_up()
1307 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET; in comphy_sfi_power_up()
1309 data |= 0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET; in comphy_sfi_power_up()
1311 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in comphy_sfi_power_up()
1313 /* 0xA-DFE_Reg3 */ in comphy_sfi_power_up()
1315 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; in comphy_sfi_power_up()
1317 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; in comphy_sfi_power_up()
1318 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in comphy_sfi_power_up()
1320 /* 0x111-G1_Setting_4 */ in comphy_sfi_power_up()
1322 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; in comphy_sfi_power_up()
1323 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in comphy_sfi_power_up()
1326 data = 0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET; in comphy_sfi_power_up()
1330 data |= 0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET; in comphy_sfi_power_up()
1332 data |= 0x4 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET; in comphy_sfi_power_up()
1334 data |= 0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET; in comphy_sfi_power_up()
1336 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in comphy_sfi_power_up()
1340 data = 0x13 << HPIPE_RX_TRAIN_TIMER_OFFSET; in comphy_sfi_power_up()
1341 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in comphy_sfi_power_up()
1345 data = 0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET; in comphy_sfi_power_up()
1346 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in comphy_sfi_power_up()
1350 data = 0x2 << HPIPE_TX_PRESET_INDEX_OFFSET; in comphy_sfi_power_up()
1351 reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask); in comphy_sfi_power_up()
1355 data = 0x0 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET; in comphy_sfi_power_up()
1356 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in comphy_sfi_power_up()
1360 data = 0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET; in comphy_sfi_power_up()
1362 data |= 0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET; in comphy_sfi_power_up()
1363 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in comphy_sfi_power_up()
1367 data = 0x88 << HPIPE_TRAIN_PAT_NUM_OFFSET; in comphy_sfi_power_up()
1368 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask); in comphy_sfi_power_up()
1372 data = 0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET; in comphy_sfi_power_up()
1373 reg_set(hpipe_addr + HPIPE_DME_REG, data, mask); in comphy_sfi_power_up()
1377 data = 0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET; in comphy_sfi_power_up()
1378 reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask); in comphy_sfi_power_up()
1382 data = 0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET; in comphy_sfi_power_up()
1384 data |= 0x1 << HPIPE_SMAPLER_OFFSET; in comphy_sfi_power_up()
1385 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sfi_power_up()
1387 data = 0x0 << HPIPE_SMAPLER_OFFSET; in comphy_sfi_power_up()
1388 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sfi_power_up()
1392 data = 0x1A << HPIPE_EXT_SELLV_RXSAMPL_OFFSET; in comphy_sfi_power_up()
1393 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in comphy_sfi_power_up()
1395 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); in comphy_sfi_power_up()
1398 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_sfi_power_up()
1400 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_sfi_power_up()
1402 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_sfi_power_up()
1403 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sfi_power_up()
1408 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | in comphy_sfi_power_up()
1410 mask = data; in comphy_sfi_power_up()
1411 data = polling_with_timeout(addr, data, mask, 15000); in comphy_sfi_power_up()
1412 if (data != 0) { in comphy_sfi_power_up()
1413 debug("Read from reg = %p - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sfi_power_up()
1415 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), in comphy_sfi_power_up()
1416 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); in comphy_sfi_power_up()
1422 data = 0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in comphy_sfi_power_up()
1423 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1428 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; in comphy_sfi_power_up()
1429 mask = data; in comphy_sfi_power_up()
1430 data = polling_with_timeout(addr, data, mask, 100); in comphy_sfi_power_up()
1431 if (data != 0) { in comphy_sfi_power_up()
1432 debug("Read from reg = %p - value = 0x%x\n", in comphy_sfi_power_up()
1433 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_sfi_power_up()
1441 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in comphy_sfi_power_up()
1443 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_sfi_power_up()
1444 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1453 u32 mask, data, ret = 1; in comphy_rxauii_power_up() local
1460 debug("stage: RFU configurations - hard reset comphy\n"); in comphy_rxauii_power_up()
1461 /* RFU configurations - hard reset comphy */ in comphy_rxauii_power_up()
1463 data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET; in comphy_rxauii_power_up()
1465 data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET; in comphy_rxauii_power_up()
1466 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_rxauii_power_up()
1481 data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_rxauii_power_up()
1483 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET; in comphy_rxauii_power_up()
1485 data |= 0xB << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET; in comphy_rxauii_power_up()
1487 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_rxauii_power_up()
1489 data |= 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_rxauii_power_up()
1491 data |= 0x0 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET; in comphy_rxauii_power_up()
1493 data |= 0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET; in comphy_rxauii_power_up()
1494 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_rxauii_power_up()
1498 data = 0x0 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_rxauii_power_up()
1500 data |= 0x0 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_rxauii_power_up()
1502 data |= 0x0 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_rxauii_power_up()
1503 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_rxauii_power_up()
1506 data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET; in comphy_rxauii_power_up()
1508 data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET; in comphy_rxauii_power_up()
1509 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_rxauii_power_up()
1511 /* Wait 1ms - until band gap and ref clock ready */ in comphy_rxauii_power_up()
1522 data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; in comphy_rxauii_power_up()
1524 data |= 0x4 << HPIPE_PWR_PLL_PHY_MODE_OFFSET; in comphy_rxauii_power_up()
1525 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_rxauii_power_up()
1531 data = 0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET; in comphy_rxauii_power_up()
1533 data |= 0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET; in comphy_rxauii_power_up()
1534 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in comphy_rxauii_power_up()
1546 /* 0x7-DFE Resolution control */ in comphy_rxauii_power_up()
1549 /* 0xd-G1_Setting_0 */ in comphy_rxauii_power_up()
1553 /* 0xE-G1_Setting_1 */ in comphy_rxauii_power_up()
1555 data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; in comphy_rxauii_power_up()
1557 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; in comphy_rxauii_power_up()
1559 data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; in comphy_rxauii_power_up()
1560 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in comphy_rxauii_power_up()
1561 /* 0xA-DFE_Reg3 */ in comphy_rxauii_power_up()
1563 data = 0x0 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET; in comphy_rxauii_power_up()
1565 data |= 0x0 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET; in comphy_rxauii_power_up()
1566 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in comphy_rxauii_power_up()
1568 /* 0x111-G1_Setting_4 */ in comphy_rxauii_power_up()
1570 data = 0x1 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET; in comphy_rxauii_power_up()
1571 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in comphy_rxauii_power_up()
1573 debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); in comphy_rxauii_power_up()
1576 data = 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET; in comphy_rxauii_power_up()
1578 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET; in comphy_rxauii_power_up()
1580 data |= 0x1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET; in comphy_rxauii_power_up()
1581 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_rxauii_power_up()
1586 data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | in comphy_rxauii_power_up()
1588 mask = data; in comphy_rxauii_power_up()
1589 data = polling_with_timeout(addr, data, mask, 15000); in comphy_rxauii_power_up()
1590 if (data != 0) { in comphy_rxauii_power_up()
1591 debug("Read from reg = %p - value = 0x%x\n", in comphy_rxauii_power_up()
1592 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_rxauii_power_up()
1594 (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), in comphy_rxauii_power_up()
1595 (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); in comphy_rxauii_power_up()
1606 data = SD_EXTERNAL_STATUS0_RX_INIT_MASK; in comphy_rxauii_power_up()
1607 mask = data; in comphy_rxauii_power_up()
1608 data = polling_with_timeout(addr, data, mask, 100); in comphy_rxauii_power_up()
1609 if (data != 0) { in comphy_rxauii_power_up()
1610 debug("Read from reg = %p - value = 0x%x\n", in comphy_rxauii_power_up()
1611 sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); in comphy_rxauii_power_up()
1619 data = 0x0 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET; in comphy_rxauii_power_up()
1621 data |= 0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET; in comphy_rxauii_power_up()
1622 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_rxauii_power_up()
1633 u32 mask, data; in comphy_utmi_power_down() local
1636 debug("stage: UTMI %d - Power down transceiver (power down Phy), Power down PLL, and SuspendDM\n", in comphy_utmi_power_down()
1643 * If UTMI connected to USB Device, configure mux prior to PHY init in comphy_utmi_power_down()
1647 debug("stage: UTMI %d - Enable Device mode and configure UTMI mux\n", in comphy_utmi_power_down()
1651 data = 0x1 << UTMI_USB_CFG_DEVICE_EN_OFFSET; in comphy_utmi_power_down()
1652 /* USB3 Device UTMI MUX */ in comphy_utmi_power_down()
1654 data |= utmi_index << UTMI_USB_CFG_DEVICE_MUX_OFFSET; in comphy_utmi_power_down()
1655 reg_set(usb_cfg_addr, data, mask); in comphy_utmi_power_down()
1660 data = 0x1 << UTMI_CTRL_STATUS0_SUSPENDM_OFFSET; in comphy_utmi_power_down()
1663 data |= 0x1 << UTMI_CTRL_STATUS0_TEST_SEL_OFFSET; in comphy_utmi_power_down()
1664 reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask); in comphy_utmi_power_down()
1678 u32 mask, data; in comphy_utmi_phy_config() local
1684 data = 0x5 << UTMI_PLL_CTRL_REFDIV_OFFSET; in comphy_utmi_phy_config()
1685 /* Feedback Clock Divider Select - 90 for 25Mhz*/ in comphy_utmi_phy_config()
1687 data |= 0x60 << UTMI_PLL_CTRL_FBDIV_OFFSET; in comphy_utmi_phy_config()
1688 /* Select LPFR - 0x0 for 25Mhz/5=5Mhz*/ in comphy_utmi_phy_config()
1690 data |= 0x0 << UTMI_PLL_CTRL_SEL_LPFR_OFFSET; in comphy_utmi_phy_config()
1691 reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask); in comphy_utmi_phy_config()
1700 data = 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; in comphy_utmi_phy_config()
1703 data |= 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; in comphy_utmi_phy_config()
1704 reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask); in comphy_utmi_phy_config()
1708 data = 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; in comphy_utmi_phy_config()
1711 data |= 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; in comphy_utmi_phy_config()
1712 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask); in comphy_utmi_phy_config()
1716 data = 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET; in comphy_utmi_phy_config()
1719 data |= 0x1 << UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET; in comphy_utmi_phy_config()
1720 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask); in comphy_utmi_phy_config()
1722 /* Set Control VDAT Reference Voltage - 0.325V */ in comphy_utmi_phy_config()
1724 data = 0x1 << UTMI_CHGDTC_CTRL_VDAT_OFFSET; in comphy_utmi_phy_config()
1725 /* Set Control VSRC Reference Voltage - 0.6V */ in comphy_utmi_phy_config()
1727 data |= 0x1 << UTMI_CHGDTC_CTRL_VSRC_OFFSET; in comphy_utmi_phy_config()
1728 reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask); in comphy_utmi_phy_config()
1738 u32 data, mask, ret = 1; in comphy_utmi_power_up() local
1742 debug("stage: UTMI %d - Power up transceiver(Power up Phy), and exit SuspendDM\n", in comphy_utmi_power_up()
1754 data = UTMI_CALIB_CTRL_IMPCAL_DONE_MASK; in comphy_utmi_power_up()
1755 mask = data; in comphy_utmi_power_up()
1756 data = polling_with_timeout(addr, data, mask, 100); in comphy_utmi_power_up()
1757 if (data != 0) { in comphy_utmi_power_up()
1759 debug("Read from reg = %p - value = 0x%x\n", addr, data); in comphy_utmi_power_up()
1763 data = UTMI_CALIB_CTRL_PLLCAL_DONE_MASK; in comphy_utmi_power_up()
1764 mask = data; in comphy_utmi_power_up()
1765 data = polling_with_timeout(addr, data, mask, 100); in comphy_utmi_power_up()
1766 if (data != 0) { in comphy_utmi_power_up()
1768 debug("Read from reg = %p - value = 0x%x\n", addr, data); in comphy_utmi_power_up()
1773 data = UTMI_PLL_CTRL_PLL_RDY_MASK; in comphy_utmi_power_up()
1774 mask = data; in comphy_utmi_power_up()
1775 data = polling_with_timeout(addr, data, mask, 100); in comphy_utmi_power_up()
1776 if (data != 0) { in comphy_utmi_power_up()
1778 debug("Read from reg = %p - value = 0x%x\n", addr, data); in comphy_utmi_power_up()
1797 * Note: - Power down/up should be once for both UTMI PHYs
1798 * - comphy_dedicated_phys_init call this function if at least there is
1858 * - not muxed SerDes lanes e.g. UTMI PHY
1870 node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, in comphy_dedicated_phys_init()
1871 "marvell,mvebu-utmi-2.6.0"); in comphy_dedicated_phys_init()
1878 gd->fdt_blob, node, "reg", 0, NULL, true); in comphy_dedicated_phys_init()
1888 gd->fdt_blob, node, "reg", 1, NULL, true); in comphy_dedicated_phys_init()
1898 gd->fdt_blob, node, "reg", 2, NULL, true); in comphy_dedicated_phys_init()
1910 gd->fdt_blob, node, "utmi-port", UTMI_PHY_INVALID); in comphy_dedicated_phys_init()
1918 gd->fdt_blob, node, "marvell,mvebu-utmi-2.6.0"); in comphy_dedicated_phys_init()
1936 comphy_max_count = ptr_chip_cfg->comphy_lanes_count; in comphy_mux_cp110_init()
1937 comphy_base_addr = ptr_chip_cfg->comphy_base_addr; in comphy_mux_cp110_init()
1952 ptr_chip_cfg->mux_data = cp110_comphy_phy_mux_data; in comphy_mux_cp110_init()
1956 ptr_chip_cfg->mux_data = cp110_comphy_pipe_mux_data; in comphy_mux_cp110_init()
1977 comphy_max_count = ptr_chip_cfg->comphy_lanes_count; in comphy_cp110_init()
1978 comphy_base_addr = ptr_chip_cfg->comphy_base_addr; in comphy_cp110_init()
1979 hpipe_base_addr = ptr_chip_cfg->hpipe3_base_addr; in comphy_cp110_init()
1981 /* Config Comphy mux configuration */ in comphy_cp110_init()
1984 /* Check if the first 4 lanes configured as By-4 */ in comphy_cp110_init()
1987 if (ptr_comphy_map->type != PHY_TYPE_PEX0) in comphy_cp110_init()
1995 debug("Serdes type = 0x%x\n", ptr_comphy_map->type); in comphy_cp110_init()
2003 switch (ptr_comphy_map->type) { in comphy_cp110_init()
2013 lane, pcie_width, ptr_comphy_map->clk_src, in comphy_cp110_init()
2014 serdes_map->end_point, in comphy_cp110_init()
2023 ptr_chip_cfg->cp_index, in comphy_cp110_init()
2036 if (ptr_comphy_map->speed == PHY_SPEED_INVALID) { in comphy_cp110_init()
2039 ptr_comphy_map->speed = PHY_SPEED_1_25G; in comphy_cp110_init()
2042 lane, ptr_comphy_map->speed, hpipe_base_addr, in comphy_cp110_init()
2048 ptr_comphy_map->speed); in comphy_cp110_init()
2065 ptr_comphy_map->type = PHY_TYPE_UNCONNECTED; in comphy_cp110_init()
2066 pr_err("PLL is not locked - Failed to initialize lane %d\n", in comphy_cp110_init()