Lines Matching full:mask
71 u32 mask, unsigned long usec_timout) in polling_with_timeout() argument
77 data = readl(addr) & mask; in polling_with_timeout()
90 u32 mask, data, ret = 1; in comphy_pcie_power_up() local
137 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in comphy_pcie_power_up()
139 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in comphy_pcie_power_up()
141 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in comphy_pcie_power_up()
143 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in comphy_pcie_power_up()
145 mask |= COMMON_PHY_PHY_MODE_MASK; in comphy_pcie_power_up()
147 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
150 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in comphy_pcie_power_up()
152 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in comphy_pcie_power_up()
154 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_pcie_power_up()
161 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; in comphy_pcie_power_up()
164 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; in comphy_pcie_power_up()
167 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; in comphy_pcie_power_up()
170 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; in comphy_pcie_power_up()
172 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in comphy_pcie_power_up()
175 mask = HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK; in comphy_pcie_power_up()
178 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK; in comphy_pcie_power_up()
180 mask |= HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK; in comphy_pcie_power_up()
182 reg_set(hpipe_addr + HPIPE_CLK_SRC_LO_REG, data, mask); in comphy_pcie_power_up()
186 mask = HPIPE_CLK_SRC_HI_MODE_PIPE_MASK; in comphy_pcie_power_up()
188 mask |= HPIPE_CLK_SRC_HI_LANE_STRT_MASK; in comphy_pcie_power_up()
189 mask |= HPIPE_CLK_SRC_HI_LANE_MASTER_MASK; in comphy_pcie_power_up()
190 mask |= HPIPE_CLK_SRC_HI_LANE_BREAK_MASK; in comphy_pcie_power_up()
198 reg_set(hpipe_addr + HPIPE_CLK_SRC_HI_REG, data, mask); in comphy_pcie_power_up()
209 mask = 0; in comphy_pcie_power_up()
213 mask |= HPIPE_MISC_CLK100M_125M_MASK; in comphy_pcie_power_up()
220 mask |= HPIPE_MISC_TXDCLK_2X_MASK; in comphy_pcie_power_up()
223 mask |= HPIPE_MISC_CLK500_EN_MASK; in comphy_pcie_power_up()
227 mask |= HPIPE_MISC_REFCLK_SEL_MASK; in comphy_pcie_power_up()
231 mask |= HPIPE_MISC_REFCLK_SEL_MASK; in comphy_pcie_power_up()
234 mask |= HPIPE_MISC_ICP_FORCE_MASK; in comphy_pcie_power_up()
236 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in comphy_pcie_power_up()
239 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in comphy_pcie_power_up()
243 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in comphy_pcie_power_up()
247 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in comphy_pcie_power_up()
249 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_pcie_power_up()
253 mask = HPIPE_LANE_ALIGN_OFF_MASK; in comphy_pcie_power_up()
255 reg_set(hpipe_addr + HPIPE_LANE_ALIGN_REG, data, mask); in comphy_pcie_power_up()
269 mask = HPIPE_INTERFACE_GEN_MAX_MASK; in comphy_pcie_power_up()
272 mask = HPIPE_INTERFACE_DET_BYPASS_MASK; in comphy_pcie_power_up()
275 mask |= HPIPE_INTERFACE_LINK_TRAIN_MASK; in comphy_pcie_power_up()
277 reg_set(hpipe_addr + HPIPE_INTERFACE_REG, data, mask); in comphy_pcie_power_up()
280 mask = HPIPE_PCIE_IDLE_SYNC_MASK; in comphy_pcie_power_up()
283 mask |= HPIPE_PCIE_SEL_BITS_MASK; in comphy_pcie_power_up()
285 reg_set(hpipe_addr + HPIPE_PCIE_REG0, data, mask); in comphy_pcie_power_up()
288 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK; in comphy_pcie_power_up()
291 mask |= HPIPE_TX_TRAIN_CTRL_GN1_MASK; in comphy_pcie_power_up()
294 mask |= HPIPE_TX_TRAIN_CTRL_G0_MASK; in comphy_pcie_power_up()
296 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in comphy_pcie_power_up()
299 mask = HPIPE_TX_TRAIN_CHK_INIT_MASK; in comphy_pcie_power_up()
302 mask |= HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK; in comphy_pcie_power_up()
304 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in comphy_pcie_power_up()
308 mask = HPIPE_TX_TX_STATUS_CHECK_MODE_MASK; in comphy_pcie_power_up()
311 mask |= HPIPE_TX_NUM_OF_PRESET_MASK; in comphy_pcie_power_up()
314 mask |= HPIPE_TX_SWEEP_PRESET_EN_MASK; in comphy_pcie_power_up()
316 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_11_REG, data, mask); in comphy_pcie_power_up()
319 mask = HPIPE_TX_TRAIN_START_SQ_EN_MASK; in comphy_pcie_power_up()
322 mask |= HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK; in comphy_pcie_power_up()
325 mask |= HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK; in comphy_pcie_power_up()
328 mask |= HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK; in comphy_pcie_power_up()
330 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in comphy_pcie_power_up()
333 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; in comphy_pcie_power_up()
335 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in comphy_pcie_power_up()
338 mask = HPIPE_TRX_TRAIN_TIMER_MASK; in comphy_pcie_power_up()
340 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_4_REG, data, mask); in comphy_pcie_power_up()
343 mask = HPIPE_TX_TRAIN_CTRL_G1_MASK | HPIPE_TX_TRAIN_CTRL_GN1_MASK in comphy_pcie_power_up()
346 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_REG, data, mask); in comphy_pcie_power_up()
349 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in comphy_pcie_power_up()
351 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_pcie_power_up()
354 mask = HPIPE_G3_DFE_RES_MASK; in comphy_pcie_power_up()
356 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in comphy_pcie_power_up()
359 mask = HPIPE_DFE_RES_FORCE_MASK; in comphy_pcie_power_up()
361 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in comphy_pcie_power_up()
364 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; in comphy_pcie_power_up()
367 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; in comphy_pcie_power_up()
370 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; in comphy_pcie_power_up()
372 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in comphy_pcie_power_up()
375 mask = HPIPE_SMAPLER_MASK; in comphy_pcie_power_up()
377 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_pcie_power_up()
379 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, 0, mask); in comphy_pcie_power_up()
382 mask = HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; in comphy_pcie_power_up()
385 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; in comphy_pcie_power_up()
387 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in comphy_pcie_power_up()
390 mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; in comphy_pcie_power_up()
392 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in comphy_pcie_power_up()
395 mask = HPIPE_CDR_MAX_DFE_ADAPT_1_MASK; in comphy_pcie_power_up()
397 mask |= HPIPE_CDR_MAX_DFE_ADAPT_0_MASK; in comphy_pcie_power_up()
399 mask |= HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK; in comphy_pcie_power_up()
401 reg_set(hpipe_addr + HPIPE_CDR_CONTROL_REG, data, mask); in comphy_pcie_power_up()
402 mask = HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK; in comphy_pcie_power_up()
404 reg_set(hpipe_addr + HPIPE_DFE_CONTROL_REG, data, mask); in comphy_pcie_power_up()
407 mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; in comphy_pcie_power_up()
409 mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; in comphy_pcie_power_up()
411 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; in comphy_pcie_power_up()
413 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in comphy_pcie_power_up()
416 mask = HPIPE_G2_DFE_RES_MASK; in comphy_pcie_power_up()
418 reg_set(hpipe_addr + HPIPE_G2_SETTINGS_4_REG, data, mask); in comphy_pcie_power_up()
421 mask = HPIPE_LANE_CFG4_DFE_EN_SEL_MASK; in comphy_pcie_power_up()
423 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in comphy_pcie_power_up()
426 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; in comphy_pcie_power_up()
428 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in comphy_pcie_power_up()
431 mask = HPIPE_G3_SETTING_5_G3_ICP_MASK; in comphy_pcie_power_up()
433 reg_set(hpipe_addr + HPIPE_G3_SETTING_5_REG, data, mask); in comphy_pcie_power_up()
436 mask = HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK; in comphy_pcie_power_up()
438 mask |= HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK; in comphy_pcie_power_up()
440 mask |= HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK; in comphy_pcie_power_up()
442 reg_set(hpipe_addr + HPIPE_LANE_EQ_REMOTE_SETTING_REG, data, mask); in comphy_pcie_power_up()
446 mask = HPIPE_CFG_PHY_RC_EP_MASK; in comphy_pcie_power_up()
448 reg_set(hpipe_addr + HPIPE_LANE_EQU_CONFIG_0_REG, data, mask); in comphy_pcie_power_up()
505 mask = data; in comphy_pcie_power_up()
506 data = polling_with_timeout(addr, data, mask, 15000); in comphy_pcie_power_up()
524 u32 mask, data, ret = 1; in comphy_usb3_power_up() local
532 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in comphy_usb3_power_up()
534 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in comphy_usb3_power_up()
536 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in comphy_usb3_power_up()
538 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in comphy_usb3_power_up()
540 mask |= COMMON_PHY_PHY_MODE_MASK; in comphy_usb3_power_up()
542 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_usb3_power_up()
545 mask = COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in comphy_usb3_power_up()
547 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in comphy_usb3_power_up()
549 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_usb3_power_up()
557 mask = HPIPE_RST_CLK_CTRL_PIPE_RST_MASK; in comphy_usb3_power_up()
560 mask |= HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK; in comphy_usb3_power_up()
563 mask |= HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK; in comphy_usb3_power_up()
566 mask |= HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK; in comphy_usb3_power_up()
568 reg_set(hpipe_addr + HPIPE_RST_CLK_CTRL_REG, data, mask); in comphy_usb3_power_up()
578 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in comphy_usb3_power_up()
581 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in comphy_usb3_power_up()
583 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_usb3_power_up()
608 mask = HPIPE_LANE_CFG4_DFE_CTRL_MASK; in comphy_usb3_power_up()
611 mask |= HPIPE_LANE_CFG4_DFE_OVER_MASK; in comphy_usb3_power_up()
614 mask |= HPIPE_LANE_CFG4_SSC_CTRL_MASK; in comphy_usb3_power_up()
616 reg_set(hpipe_addr + HPIPE_LANE_CFG4_REG, data, mask); in comphy_usb3_power_up()
630 mask = data; in comphy_usb3_power_up()
631 data = polling_with_timeout(addr, data, mask, 15000); in comphy_usb3_power_up()
647 u32 mask, data, i, ret = 1; in comphy_sata_power_up() local
691 mask = SATA3_CTRL_SATA0_PD_MASK; in comphy_sata_power_up()
694 mask |= SATA3_CTRL_SATA1_PD_MASK; in comphy_sata_power_up()
697 mask |= SATA3_CTRL_SATA1_ENABLE_MASK; in comphy_sata_power_up()
700 mask |= SATA3_CTRL_SATA_SSU_MASK; in comphy_sata_power_up()
702 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); in comphy_sata_power_up()
706 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in comphy_sata_power_up()
708 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in comphy_sata_power_up()
710 mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK; in comphy_sata_power_up()
712 mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK; in comphy_sata_power_up()
714 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_sata_power_up()
722 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in comphy_sata_power_up()
724 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in comphy_sata_power_up()
726 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sata_power_up()
738 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in comphy_sata_power_up()
741 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in comphy_sata_power_up()
743 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_sata_power_up()
755 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in comphy_sata_power_up()
757 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; in comphy_sata_power_up()
759 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; in comphy_sata_power_up()
761 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; in comphy_sata_power_up()
763 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; in comphy_sata_power_up()
765 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in comphy_sata_power_up()
767 mask = HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; in comphy_sata_power_up()
769 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; in comphy_sata_power_up()
771 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; in comphy_sata_power_up()
773 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK; in comphy_sata_power_up()
775 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK; in comphy_sata_power_up()
777 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in comphy_sata_power_up()
780 mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; in comphy_sata_power_up()
782 mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; in comphy_sata_power_up()
784 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; in comphy_sata_power_up()
786 mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK; in comphy_sata_power_up()
788 mask |= HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK; in comphy_sata_power_up()
790 reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); in comphy_sata_power_up()
793 mask = HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK; in comphy_sata_power_up()
795 mask |= HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK; in comphy_sata_power_up()
797 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK; in comphy_sata_power_up()
799 mask |= HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK; in comphy_sata_power_up()
801 mask |= HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK; in comphy_sata_power_up()
803 mask |= HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK; in comphy_sata_power_up()
805 mask |= HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK; in comphy_sata_power_up()
807 reg_set(hpipe_addr + HPIPE_G3_SET_1_REG, data, mask); in comphy_sata_power_up()
810 mask = HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK; in comphy_sata_power_up()
812 mask |= HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK; in comphy_sata_power_up()
814 mask |= HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in comphy_sata_power_up()
816 mask |= HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK; in comphy_sata_power_up()
818 mask |= HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK; in comphy_sata_power_up()
820 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_MASK; in comphy_sata_power_up()
822 mask |= HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK; in comphy_sata_power_up()
824 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_sata_power_up()
827 mask = HPIPE_SMAPLER_MASK; in comphy_sata_power_up()
829 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sata_power_up()
830 mask = HPIPE_SMAPLER_MASK; in comphy_sata_power_up()
832 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sata_power_up()
835 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; in comphy_sata_power_up()
837 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in comphy_sata_power_up()
840 mask = HPIPE_DFE_RES_FORCE_MASK; in comphy_sata_power_up()
842 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in comphy_sata_power_up()
845 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; in comphy_sata_power_up()
847 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; in comphy_sata_power_up()
849 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in comphy_sata_power_up()
852 mask = HPIPE_G3_FFE_CAP_SEL_MASK; in comphy_sata_power_up()
854 mask |= HPIPE_G3_FFE_RES_SEL_MASK; in comphy_sata_power_up()
856 mask |= HPIPE_G3_FFE_SETTING_FORCE_MASK; in comphy_sata_power_up()
858 mask |= HPIPE_G3_FFE_DEG_RES_LEVEL_MASK; in comphy_sata_power_up()
860 mask |= HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK; in comphy_sata_power_up()
862 reg_set(hpipe_addr + HPIPE_G3_SETTING_3_REG, data, mask); in comphy_sata_power_up()
865 mask = HPIPE_G3_DFE_RES_MASK; in comphy_sata_power_up()
867 reg_set(hpipe_addr + HPIPE_G3_SETTING_4_REG, data, mask); in comphy_sata_power_up()
870 mask = HPIPE_OS_PH_OFFSET_MASK; in comphy_sata_power_up()
872 mask |= HPIPE_OS_PH_OFFSET_FORCE_MASK; in comphy_sata_power_up()
874 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in comphy_sata_power_up()
875 mask = HPIPE_OS_PH_VALID_MASK; in comphy_sata_power_up()
877 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in comphy_sata_power_up()
878 mask = HPIPE_OS_PH_VALID_MASK; in comphy_sata_power_up()
880 reg_set(hpipe_addr + HPIPE_PHASE_CONTROL_REG, data, mask); in comphy_sata_power_up()
883 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; in comphy_sata_power_up()
885 mask |= HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK; in comphy_sata_power_up()
887 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; in comphy_sata_power_up()
889 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK; in comphy_sata_power_up()
891 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in comphy_sata_power_up()
894 mask = HPIPE_G2_SET_0_G2_TX_AMP_MASK; in comphy_sata_power_up()
896 mask |= HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK; in comphy_sata_power_up()
898 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_MASK; in comphy_sata_power_up()
900 mask |= HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK; in comphy_sata_power_up()
902 reg_set(hpipe_addr + HPIPE_G2_SET_0_REG, data, mask); in comphy_sata_power_up()
905 mask = HPIPE_G3_SET_0_G3_TX_AMP_MASK; in comphy_sata_power_up()
907 mask |= HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK; in comphy_sata_power_up()
909 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_MASK; in comphy_sata_power_up()
911 mask |= HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK; in comphy_sata_power_up()
913 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK; in comphy_sata_power_up()
915 mask |= HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK; in comphy_sata_power_up()
917 reg_set(hpipe_addr + HPIPE_G3_SET_0_REG, data, mask); in comphy_sata_power_up()
920 mask = SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK; in comphy_sata_power_up()
922 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in comphy_sata_power_up()
933 data = mask = 0; in comphy_sata_power_up()
936 mask |= HPIPE_SYNC_PATTERN_TXD_SWAP_MASK; in comphy_sata_power_up()
940 mask |= HPIPE_SYNC_PATTERN_RXD_SWAP_MASK; in comphy_sata_power_up()
942 reg_set(hpipe_addr + HPIPE_SYNC_PATTERN_REG, data, mask); in comphy_sata_power_up()
961 mask = SATA3_CTRL_SATA0_PD_MASK; in comphy_sata_power_up()
964 mask |= SATA3_CTRL_SATA1_PD_MASK; in comphy_sata_power_up()
967 mask |= SATA3_CTRL_SATA1_ENABLE_MASK; in comphy_sata_power_up()
970 mask |= SATA3_CTRL_SATA_SSU_MASK; in comphy_sata_power_up()
972 reg_set(sata_base + SATA3_VENDOR_DATA, data, mask); in comphy_sata_power_up()
987 mask = data; in comphy_sata_power_up()
988 data = polling_with_timeout(addr, data, mask, 15000); in comphy_sata_power_up()
1006 u32 mask, data, ret = 1; in comphy_sgmii_power_up() local
1015 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in comphy_sgmii_power_up()
1017 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in comphy_sgmii_power_up()
1019 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_sgmii_power_up()
1022 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in comphy_sgmii_power_up()
1024 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; in comphy_sgmii_power_up()
1025 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; in comphy_sgmii_power_up()
1034 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in comphy_sgmii_power_up()
1036 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in comphy_sgmii_power_up()
1038 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; in comphy_sgmii_power_up()
1040 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sgmii_power_up()
1043 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in comphy_sgmii_power_up()
1045 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in comphy_sgmii_power_up()
1047 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in comphy_sgmii_power_up()
1049 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1052 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in comphy_sgmii_power_up()
1054 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in comphy_sgmii_power_up()
1056 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1065 mask = HPIPE_MISC_REFCLK_SEL_MASK; in comphy_sgmii_power_up()
1067 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in comphy_sgmii_power_up()
1069 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in comphy_sgmii_power_up()
1071 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in comphy_sgmii_power_up()
1073 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_sgmii_power_up()
1075 mask = HPIPE_LOOPBACK_SEL_MASK; in comphy_sgmii_power_up()
1077 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in comphy_sgmii_power_up()
1079 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; in comphy_sgmii_power_up()
1081 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; in comphy_sgmii_power_up()
1083 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in comphy_sgmii_power_up()
1085 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in comphy_sgmii_power_up()
1087 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_sgmii_power_up()
1098 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in comphy_sgmii_power_up()
1100 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in comphy_sgmii_power_up()
1102 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in comphy_sgmii_power_up()
1104 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sgmii_power_up()
1110 mask = data; in comphy_sgmii_power_up()
1111 data = polling_with_timeout(addr, data, mask, 15000); in comphy_sgmii_power_up()
1122 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in comphy_sgmii_power_up()
1124 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1129 mask = data; in comphy_sgmii_power_up()
1130 data = polling_with_timeout(addr, data, mask, 100); in comphy_sgmii_power_up()
1139 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in comphy_sgmii_power_up()
1141 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in comphy_sgmii_power_up()
1143 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sgmii_power_up()
1152 u32 mask, data, ret = 1; in comphy_sfi_power_up() local
1161 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in comphy_sfi_power_up()
1163 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in comphy_sfi_power_up()
1165 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_sfi_power_up()
1168 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in comphy_sfi_power_up()
1170 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; in comphy_sfi_power_up()
1172 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; in comphy_sfi_power_up()
1174 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in comphy_sfi_power_up()
1176 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in comphy_sfi_power_up()
1178 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; in comphy_sfi_power_up()
1180 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sfi_power_up()
1183 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in comphy_sfi_power_up()
1185 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in comphy_sfi_power_up()
1187 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in comphy_sfi_power_up()
1189 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1191 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in comphy_sfi_power_up()
1193 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in comphy_sfi_power_up()
1195 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1204 mask = HPIPE_MISC_ICP_FORCE_MASK; in comphy_sfi_power_up()
1208 mask |= HPIPE_MISC_REFCLK_SEL_MASK; in comphy_sfi_power_up()
1210 reg_set(hpipe_addr + HPIPE_MISC_REG, data, mask); in comphy_sfi_power_up()
1212 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in comphy_sfi_power_up()
1214 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in comphy_sfi_power_up()
1216 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_sfi_power_up()
1218 mask = HPIPE_LOOPBACK_SEL_MASK; in comphy_sfi_power_up()
1220 reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, data, mask); in comphy_sfi_power_up()
1222 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; in comphy_sfi_power_up()
1224 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; in comphy_sfi_power_up()
1226 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in comphy_sfi_power_up()
1228 mask = HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK; in comphy_sfi_power_up()
1230 reg_set(hpipe_addr + HPIPE_PWR_CTR_DTL_REG, data, mask); in comphy_sfi_power_up()
1234 mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK; in comphy_sfi_power_up()
1236 mask |= HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK; in comphy_sfi_power_up()
1238 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK; in comphy_sfi_power_up()
1240 mask |= HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK; in comphy_sfi_power_up()
1243 mask = HPIPE_TXDIGCK_DIV_FORCE_MASK; in comphy_sfi_power_up()
1246 reg_set(hpipe_addr + HPIPE_SPD_DIV_FORCE_REG, data, mask); in comphy_sfi_power_up()
1251 mask = SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK; in comphy_sfi_power_up()
1253 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, data, mask); in comphy_sfi_power_up()
1255 mask = HPIPE_DFE_RES_FORCE_MASK; in comphy_sfi_power_up()
1257 reg_set(hpipe_addr + HPIPE_DFE_REG0, data, mask); in comphy_sfi_power_up()
1260 mask = HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; in comphy_sfi_power_up()
1263 mask = HPIPE_G1_SET_0_G1_TX_AMP_MASK; in comphy_sfi_power_up()
1265 mask |= HPIPE_G1_SET_0_G1_TX_EMPH1_MASK; in comphy_sfi_power_up()
1268 reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, data, mask); in comphy_sfi_power_up()
1270 mask = HPIPE_G1_SET_2_G1_TX_EMPH0_MASK; in comphy_sfi_power_up()
1272 mask |= HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK; in comphy_sfi_power_up()
1274 reg_set(hpipe_addr + HPIPE_G1_SET_2_REG, data, mask); in comphy_sfi_power_up()
1276 mask = HPIPE_TX_REG1_TX_EMPH_RES_MASK; in comphy_sfi_power_up()
1278 mask |= HPIPE_TX_REG1_SLC_EN_MASK; in comphy_sfi_power_up()
1280 reg_set(hpipe_addr + HPIPE_TX_REG1_REG, data, mask); in comphy_sfi_power_up()
1282 mask = HPIPE_CAL_REG_1_EXT_TXIMP_MASK; in comphy_sfi_power_up()
1284 mask |= HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK; in comphy_sfi_power_up()
1286 reg_set(hpipe_addr + HPIPE_CAL_REG1_REG, data, mask); in comphy_sfi_power_up()
1288 mask = HPIPE_G1_SETTING_5_G1_ICP_MASK; in comphy_sfi_power_up()
1290 reg_set(hpipe_addr + HPIPE_G1_SETTING_5_REG, data, mask); in comphy_sfi_power_up()
1292 mask = HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; in comphy_sfi_power_up()
1295 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in comphy_sfi_power_up()
1297 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; in comphy_sfi_power_up()
1300 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in comphy_sfi_power_up()
1302 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; in comphy_sfi_power_up()
1304 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; in comphy_sfi_power_up()
1306 mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; in comphy_sfi_power_up()
1308 mask |= HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK; in comphy_sfi_power_up()
1311 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in comphy_sfi_power_up()
1314 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; in comphy_sfi_power_up()
1316 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; in comphy_sfi_power_up()
1318 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in comphy_sfi_power_up()
1321 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; in comphy_sfi_power_up()
1323 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in comphy_sfi_power_up()
1325 mask = HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK; in comphy_sfi_power_up()
1329 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK; in comphy_sfi_power_up()
1331 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK; in comphy_sfi_power_up()
1333 mask |= HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK; in comphy_sfi_power_up()
1336 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_3_REG, data, mask); in comphy_sfi_power_up()
1339 mask = HPIPE_RX_TRAIN_TIMER_MASK; in comphy_sfi_power_up()
1341 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_5_REG, data, mask); in comphy_sfi_power_up()
1344 mask = HPIPE_TX_TRAIN_P2P_HOLD_MASK; in comphy_sfi_power_up()
1346 reg_set(hpipe_addr + HPIPE_TX_TRAIN_CTRL_0_REG, data, mask); in comphy_sfi_power_up()
1349 mask = HPIPE_TX_PRESET_INDEX_MASK; in comphy_sfi_power_up()
1351 reg_set(hpipe_addr + HPIPE_TX_PRESET_INDEX_REG, data, mask); in comphy_sfi_power_up()
1354 mask = HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK; in comphy_sfi_power_up()
1356 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_3_REG, data, mask); in comphy_sfi_power_up()
1359 mask = HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK; in comphy_sfi_power_up()
1361 mask |= HPIPE_TX_TRAIN_PAT_SEL_MASK; in comphy_sfi_power_up()
1363 reg_set(hpipe_addr + HPIPE_TX_TRAIN_REG, data, mask); in comphy_sfi_power_up()
1366 mask = HPIPE_TRAIN_PAT_NUM_MASK; in comphy_sfi_power_up()
1368 reg_set(hpipe_addr + HPIPE_FRAME_DETECT_CTRL_0_REG, data, mask); in comphy_sfi_power_up()
1371 mask = HPIPE_DME_ETHERNET_MODE_MASK; in comphy_sfi_power_up()
1373 reg_set(hpipe_addr + HPIPE_DME_REG, data, mask); in comphy_sfi_power_up()
1376 mask = HPIPE_CAL_VDD_CONT_MODE_MASK; in comphy_sfi_power_up()
1378 reg_set(hpipe_addr + HPIPE_VDD_CAL_0_REG, data, mask); in comphy_sfi_power_up()
1381 mask = HPIPE_RX_SAMPLER_OS_GAIN_MASK; in comphy_sfi_power_up()
1383 mask |= HPIPE_SMAPLER_MASK; in comphy_sfi_power_up()
1385 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sfi_power_up()
1386 mask = HPIPE_SMAPLER_MASK; in comphy_sfi_power_up()
1388 reg_set(hpipe_addr + HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG, data, mask); in comphy_sfi_power_up()
1391 mask = HPIPE_EXT_SELLV_RXSAMPL_MASK; in comphy_sfi_power_up()
1393 reg_set(hpipe_addr + HPIPE_VDD_CAL_CTRL_REG, data, mask); in comphy_sfi_power_up()
1397 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in comphy_sfi_power_up()
1399 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in comphy_sfi_power_up()
1401 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in comphy_sfi_power_up()
1403 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_sfi_power_up()
1410 mask = data; in comphy_sfi_power_up()
1411 data = polling_with_timeout(addr, data, mask, 15000); in comphy_sfi_power_up()
1421 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in comphy_sfi_power_up()
1423 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1429 mask = data; in comphy_sfi_power_up()
1430 data = polling_with_timeout(addr, data, mask, 100); in comphy_sfi_power_up()
1440 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in comphy_sfi_power_up()
1442 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in comphy_sfi_power_up()
1444 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_sfi_power_up()
1453 u32 mask, data, ret = 1; in comphy_rxauii_power_up() local
1462 mask = COMMON_PHY_CFG1_PWR_UP_MASK; in comphy_rxauii_power_up()
1464 mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK; in comphy_rxauii_power_up()
1466 reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask); in comphy_rxauii_power_up()
1480 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in comphy_rxauii_power_up()
1482 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK; in comphy_rxauii_power_up()
1484 mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK; in comphy_rxauii_power_up()
1486 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in comphy_rxauii_power_up()
1488 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in comphy_rxauii_power_up()
1490 mask |= SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK; in comphy_rxauii_power_up()
1492 mask |= SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK; in comphy_rxauii_power_up()
1494 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_rxauii_power_up()
1497 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in comphy_rxauii_power_up()
1499 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in comphy_rxauii_power_up()
1501 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in comphy_rxauii_power_up()
1503 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_rxauii_power_up()
1505 mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; in comphy_rxauii_power_up()
1507 mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK; in comphy_rxauii_power_up()
1509 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_rxauii_power_up()
1521 mask = HPIPE_PWR_PLL_REF_FREQ_MASK; in comphy_rxauii_power_up()
1523 mask |= HPIPE_PWR_PLL_PHY_MODE_MASK; in comphy_rxauii_power_up()
1525 reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); in comphy_rxauii_power_up()
1530 mask = HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK; in comphy_rxauii_power_up()
1532 mask |= HPIPE_RX_CONTROL_1_CLK8T_EN_MASK; in comphy_rxauii_power_up()
1534 reg_set(hpipe_addr + HPIPE_RX_CONTROL_1_REG, data, mask); in comphy_rxauii_power_up()
1554 mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; in comphy_rxauii_power_up()
1556 mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; in comphy_rxauii_power_up()
1558 mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; in comphy_rxauii_power_up()
1560 reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); in comphy_rxauii_power_up()
1562 mask = HPIPE_DFE_F3_F5_DFE_EN_MASK; in comphy_rxauii_power_up()
1564 mask |= HPIPE_DFE_F3_F5_DFE_CTRL_MASK; in comphy_rxauii_power_up()
1566 reg_set(hpipe_addr + HPIPE_DFE_F3_F5_REG, data, mask); in comphy_rxauii_power_up()
1569 mask = HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK; in comphy_rxauii_power_up()
1571 reg_set(hpipe_addr + HPIPE_G1_SETTINGS_4_REG, data, mask); in comphy_rxauii_power_up()
1575 mask = SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK; in comphy_rxauii_power_up()
1577 mask |= SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK; in comphy_rxauii_power_up()
1579 mask |= SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK; in comphy_rxauii_power_up()
1581 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG0_REG, data, mask); in comphy_rxauii_power_up()
1588 mask = data; in comphy_rxauii_power_up()
1589 data = polling_with_timeout(addr, data, mask, 15000); in comphy_rxauii_power_up()
1607 mask = data; in comphy_rxauii_power_up()
1608 data = polling_with_timeout(addr, data, mask, 100); in comphy_rxauii_power_up()
1618 mask = SD_EXTERNAL_CONFIG1_RX_INIT_MASK; in comphy_rxauii_power_up()
1620 mask |= SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK; in comphy_rxauii_power_up()
1622 reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); in comphy_rxauii_power_up()
1633 u32 mask, data; in comphy_utmi_power_down() local
1650 mask = UTMI_USB_CFG_DEVICE_EN_MASK; in comphy_utmi_power_down()
1653 mask |= UTMI_USB_CFG_DEVICE_MUX_MASK; in comphy_utmi_power_down()
1655 reg_set(usb_cfg_addr, data, mask); in comphy_utmi_power_down()
1659 mask = UTMI_CTRL_STATUS0_SUSPENDM_MASK; in comphy_utmi_power_down()
1662 mask |= UTMI_CTRL_STATUS0_TEST_SEL_MASK; in comphy_utmi_power_down()
1664 reg_set(utmi_base_addr + UTMI_CTRL_STATUS0_REG, data, mask); in comphy_utmi_power_down()
1678 u32 mask, data; in comphy_utmi_phy_config() local
1683 mask = UTMI_PLL_CTRL_REFDIV_MASK; in comphy_utmi_phy_config()
1686 mask |= UTMI_PLL_CTRL_FBDIV_MASK; in comphy_utmi_phy_config()
1689 mask |= UTMI_PLL_CTRL_SEL_LPFR_MASK; in comphy_utmi_phy_config()
1691 reg_set(utmi_base_addr + UTMI_PLL_CTRL_REG, data, mask); in comphy_utmi_phy_config()
1699 mask = UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; in comphy_utmi_phy_config()
1702 mask |= UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; in comphy_utmi_phy_config()
1704 reg_set(utmi_base_addr + UTMI_TX_CH_CTRL_REG, data, mask); in comphy_utmi_phy_config()
1707 mask = UTMI_RX_CH_CTRL0_SQ_DET_MASK; in comphy_utmi_phy_config()
1710 mask |= UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; in comphy_utmi_phy_config()
1712 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL0_REG, data, mask); in comphy_utmi_phy_config()
1715 mask = UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK; in comphy_utmi_phy_config()
1718 mask |= UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK; in comphy_utmi_phy_config()
1720 reg_set(utmi_base_addr + UTMI_RX_CH_CTRL1_REG, data, mask); in comphy_utmi_phy_config()
1723 mask = UTMI_CHGDTC_CTRL_VDAT_MASK; in comphy_utmi_phy_config()
1726 mask |= UTMI_CHGDTC_CTRL_VSRC_MASK; in comphy_utmi_phy_config()
1728 reg_set(utmi_base_addr + UTMI_CHGDTC_CTRL_REG, data, mask); in comphy_utmi_phy_config()
1738 u32 data, mask, ret = 1; in comphy_utmi_power_up() local
1755 mask = data; in comphy_utmi_power_up()
1756 data = polling_with_timeout(addr, data, mask, 100); in comphy_utmi_power_up()
1764 mask = data; in comphy_utmi_power_up()
1765 data = polling_with_timeout(addr, data, mask, 100); in comphy_utmi_power_up()
1774 mask = data; in comphy_utmi_power_up()
1775 data = polling_with_timeout(addr, data, mask, 100); in comphy_utmi_power_up()