drivers/pci/pcie_xilinx.c

1 // SPDX-License-Identifier: GPL-2.0
15  * struct xilinx_pcie - Xilinx PCIe controller state
16  * @cfg_base: The base address of memory mapped configuration space
27  * pcie_xilinx_link_up() - Check whether the PCIe link is up
36 	uint32_t pscr = __raw_readl(pcie->cfg_base + XILINX_PCIE_REG_PSCR);  in pcie_xilinx_link_up()
42  * pcie_xilinx_config_address() - Calculate the address of a config access
45  * @offset: The offset into the device's configuration space
49  * configuration space access for a given device identified by the PCIe
55  * Return: 0 on success, else -ENODEV
67 		return -ENODEV;  in pcie_xilinx_config_address()
70 	 * Busses 0 (host-PCIe bridge) & 1 (its immediate child) are  in pcie_xilinx_config_address()
74 		return -ENODEV;  in pcie_xilinx_config_address()
76 	addr = pcie->cfg_base;  in pcie_xilinx_config_address()
87  * pcie_xilinx_read_config() - Read from configuration space
90  * @offset: The offset into the device's configuration space
94  * Read a value of size @size from offset @offset within the configuration
95  * space of the device identified by the bus, device & function numbers in @bdf
98  * Return: 0 on success, else -ENODEV or -EINVAL
109  * pcie_xilinx_write_config() - Write to configuration space
112  * @offset: The offset into the device's configuration space
117  * configuration space of the device identified by the bus, device & function
120  * Return: 0 on success, else -ENODEV or -EINVAL
131  * pcie_xilinx_ofdata_to_platdata() - Translate from DT to device state
138  * Return: 0 on success, else -EINVAL
147 	err = fdt_get_resource(gd->fdt_blob, dev_of_offset(dev), "reg",  in pcie_xilinx_ofdata_to_platdata()
154 	pcie->cfg_base = map_physmem(reg_res.start,  in pcie_xilinx_ofdata_to_platdata()
167 	{ .compatible = "xlnx,axi-pcie-host-1.00.a" },