Lines Matching +full:pcie +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
5 * Layerscape PCIe driver
25 static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset) in dbi_readl() argument
27 return in_le32(pcie->dbi + offset); in dbi_readl()
30 static void dbi_writel(struct ls_pcie *pcie, unsigned int value, in dbi_writel() argument
33 out_le32(pcie->dbi + offset, value); in dbi_writel()
36 static unsigned int ctrl_readl(struct ls_pcie *pcie, unsigned int offset) in ctrl_readl() argument
38 if (pcie->big_endian) in ctrl_readl()
39 return in_be32(pcie->ctrl + offset); in ctrl_readl()
41 return in_le32(pcie->ctrl + offset); in ctrl_readl()
44 static void ctrl_writel(struct ls_pcie *pcie, unsigned int value, in ctrl_writel() argument
47 if (pcie->big_endian) in ctrl_writel()
48 out_be32(pcie->ctrl + offset, value); in ctrl_writel()
50 out_le32(pcie->ctrl + offset, value); in ctrl_writel()
53 static int ls_pcie_ltssm(struct ls_pcie *pcie) in ls_pcie_ltssm() argument
60 state = ctrl_readl(pcie, LS1021_PEXMSCPORTSR(pcie->idx)); in ls_pcie_ltssm()
63 state = ctrl_readl(pcie, PCIE_PF_DBG) & LTSSM_STATE_MASK; in ls_pcie_ltssm()
69 static int ls_pcie_link_up(struct ls_pcie *pcie) in ls_pcie_link_up() argument
73 ltssm = ls_pcie_ltssm(pcie); in ls_pcie_link_up()
80 static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev) in ls_pcie_cfg0_set_busdev() argument
82 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, in ls_pcie_cfg0_set_busdev()
84 dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET); in ls_pcie_cfg0_set_busdev()
87 static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev) in ls_pcie_cfg1_set_busdev() argument
89 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, in ls_pcie_cfg1_set_busdev()
91 dbi_writel(pcie, busdev, PCIE_ATU_LOWER_TARGET); in ls_pcie_cfg1_set_busdev()
94 static void ls_pcie_atu_outbound_set(struct ls_pcie *pcie, int idx, int type, in ls_pcie_atu_outbound_set() argument
97 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | idx, PCIE_ATU_VIEWPORT); in ls_pcie_atu_outbound_set()
98 dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_BASE); in ls_pcie_atu_outbound_set()
99 dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_BASE); in ls_pcie_atu_outbound_set()
100 dbi_writel(pcie, (u32)phys + size - 1, PCIE_ATU_LIMIT); in ls_pcie_atu_outbound_set()
101 dbi_writel(pcie, (u32)bus_addr, PCIE_ATU_LOWER_TARGET); in ls_pcie_atu_outbound_set()
102 dbi_writel(pcie, bus_addr >> 32, PCIE_ATU_UPPER_TARGET); in ls_pcie_atu_outbound_set()
103 dbi_writel(pcie, type, PCIE_ATU_CR1); in ls_pcie_atu_outbound_set()
104 dbi_writel(pcie, PCIE_ATU_ENABLE, PCIE_ATU_CR2); in ls_pcie_atu_outbound_set()
108 static void ls_pcie_atu_inbound_set(struct ls_pcie *pcie, int idx, in ls_pcie_atu_inbound_set() argument
111 dbi_writel(pcie, PCIE_ATU_REGION_INBOUND | idx, PCIE_ATU_VIEWPORT); in ls_pcie_atu_inbound_set()
112 dbi_writel(pcie, (u32)phys, PCIE_ATU_LOWER_TARGET); in ls_pcie_atu_inbound_set()
113 dbi_writel(pcie, phys >> 32, PCIE_ATU_UPPER_TARGET); in ls_pcie_atu_inbound_set()
114 dbi_writel(pcie, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); in ls_pcie_atu_inbound_set()
115 dbi_writel(pcie, PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE | in ls_pcie_atu_inbound_set()
119 static void ls_pcie_dump_atu(struct ls_pcie *pcie) in ls_pcie_dump_atu() argument
124 dbi_writel(pcie, PCIE_ATU_REGION_OUTBOUND | i, in ls_pcie_dump_atu()
128 dbi_readl(pcie, PCIE_ATU_LOWER_BASE)); in ls_pcie_dump_atu()
130 dbi_readl(pcie, PCIE_ATU_UPPER_BASE)); in ls_pcie_dump_atu()
132 dbi_readl(pcie, PCIE_ATU_LOWER_TARGET)); in ls_pcie_dump_atu()
134 dbi_readl(pcie, PCIE_ATU_UPPER_TARGET)); in ls_pcie_dump_atu()
136 readl(pcie->dbi + PCIE_ATU_LIMIT)); in ls_pcie_dump_atu()
138 dbi_readl(pcie, PCIE_ATU_CR1)); in ls_pcie_dump_atu()
140 dbi_readl(pcie, PCIE_ATU_CR2)); in ls_pcie_dump_atu()
144 static void ls_pcie_setup_atu(struct ls_pcie *pcie) in ls_pcie_setup_atu() argument
154 LS1021_PCIE_SPACE_SIZE * pcie->idx; in ls_pcie_setup_atu()
158 ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0, in ls_pcie_setup_atu()
160 pcie->cfg_res.start + offset, in ls_pcie_setup_atu()
162 fdt_resource_size(&pcie->cfg_res) / 2); in ls_pcie_setup_atu()
164 ls_pcie_atu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1, in ls_pcie_setup_atu()
166 pcie->cfg_res.start + offset + in ls_pcie_setup_atu()
167 fdt_resource_size(&pcie->cfg_res) / 2, in ls_pcie_setup_atu()
169 fdt_resource_size(&pcie->cfg_res) / 2); in ls_pcie_setup_atu()
171 pci_get_regions(pcie->bus, &io, &mem, &pref); in ls_pcie_setup_atu()
174 /* Fix the pcie memory map for LS2088A series SoCs */ in ls_pcie_setup_atu()
180 io->phys_start = (io->phys_start & in ls_pcie_setup_atu()
181 (PCIE_PHYS_SIZE - 1)) + in ls_pcie_setup_atu()
183 LS2088A_PCIE_PHYS_SIZE * pcie->idx; in ls_pcie_setup_atu()
185 mem->phys_start = (mem->phys_start & in ls_pcie_setup_atu()
186 (PCIE_PHYS_SIZE - 1)) + in ls_pcie_setup_atu()
188 LS2088A_PCIE_PHYS_SIZE * pcie->idx; in ls_pcie_setup_atu()
190 pref->phys_start = (pref->phys_start & in ls_pcie_setup_atu()
191 (PCIE_PHYS_SIZE - 1)) + in ls_pcie_setup_atu()
193 LS2088A_PCIE_PHYS_SIZE * pcie->idx; in ls_pcie_setup_atu()
198 ls_pcie_atu_outbound_set(pcie, idx++, in ls_pcie_setup_atu()
200 io->phys_start + offset, in ls_pcie_setup_atu()
201 io->bus_start, in ls_pcie_setup_atu()
202 io->size); in ls_pcie_setup_atu()
206 ls_pcie_atu_outbound_set(pcie, idx++, in ls_pcie_setup_atu()
208 mem->phys_start + offset, in ls_pcie_setup_atu()
209 mem->bus_start, in ls_pcie_setup_atu()
210 mem->size); in ls_pcie_setup_atu()
214 ls_pcie_atu_outbound_set(pcie, idx++, in ls_pcie_setup_atu()
216 pref->phys_start + offset, in ls_pcie_setup_atu()
217 pref->bus_start, in ls_pcie_setup_atu()
218 pref->size); in ls_pcie_setup_atu()
220 ls_pcie_dump_atu(pcie); in ls_pcie_setup_atu()
223 /* Return 0 if the address is valid, -errno if not valid */
224 static int ls_pcie_addr_valid(struct ls_pcie *pcie, pci_dev_t bdf) in ls_pcie_addr_valid() argument
226 struct udevice *bus = pcie->bus; in ls_pcie_addr_valid()
228 if (pcie->mode == PCI_HEADER_TYPE_NORMAL) in ls_pcie_addr_valid()
229 return -ENODEV; in ls_pcie_addr_valid()
231 if (!pcie->enabled) in ls_pcie_addr_valid()
232 return -ENXIO; in ls_pcie_addr_valid()
234 if (PCI_BUS(bdf) < bus->seq) in ls_pcie_addr_valid()
235 return -EINVAL; in ls_pcie_addr_valid()
237 if ((PCI_BUS(bdf) > bus->seq) && (!ls_pcie_link_up(pcie))) in ls_pcie_addr_valid()
238 return -EINVAL; in ls_pcie_addr_valid()
240 if (PCI_BUS(bdf) <= (bus->seq + 1) && (PCI_DEV(bdf) > 0)) in ls_pcie_addr_valid()
241 return -EINVAL; in ls_pcie_addr_valid()
249 struct ls_pcie *pcie = dev_get_priv(bus); in ls_pcie_conf_address() local
252 if (ls_pcie_addr_valid(pcie, bdf)) in ls_pcie_conf_address()
253 return -EINVAL; in ls_pcie_conf_address()
255 if (PCI_BUS(bdf) == bus->seq) { in ls_pcie_conf_address()
256 *paddress = pcie->dbi + offset; in ls_pcie_conf_address()
260 busdev = PCIE_ATU_BUS(PCI_BUS(bdf) - bus->seq) | in ls_pcie_conf_address()
264 if (PCI_BUS(bdf) == bus->seq + 1) { in ls_pcie_conf_address()
265 ls_pcie_cfg0_set_busdev(pcie, busdev); in ls_pcie_conf_address()
266 *paddress = pcie->cfg0 + offset; in ls_pcie_conf_address()
268 ls_pcie_cfg1_set_busdev(pcie, busdev); in ls_pcie_conf_address()
269 *paddress = pcie->cfg1 + offset; in ls_pcie_conf_address()
290 /* Clear multi-function bit */
291 static void ls_pcie_clear_multifunction(struct ls_pcie *pcie) in ls_pcie_clear_multifunction() argument
293 writeb(PCI_HEADER_TYPE_BRIDGE, pcie->dbi + PCI_HEADER_TYPE); in ls_pcie_clear_multifunction()
297 static void ls_pcie_fix_class(struct ls_pcie *pcie) in ls_pcie_fix_class() argument
299 writew(PCI_CLASS_BRIDGE_PCI, pcie->dbi + PCI_CLASS_DEVICE); in ls_pcie_fix_class()
303 static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie) in ls_pcie_drop_msg_tlp() argument
307 val = dbi_readl(pcie, PCIE_STRFMR1); in ls_pcie_drop_msg_tlp()
309 dbi_writel(pcie, val, PCIE_STRFMR1); in ls_pcie_drop_msg_tlp()
313 static void ls_pcie_disable_bars(struct ls_pcie *pcie) in ls_pcie_disable_bars() argument
317 sriov = in_le32(pcie->dbi + PCIE_SRIOV); in ls_pcie_disable_bars()
320 * TODO: For PCIe controller with SRIOV, the method to disable bars in ls_pcie_disable_bars()
326 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_0); in ls_pcie_disable_bars()
327 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_BASE_ADDRESS_1); in ls_pcie_disable_bars()
328 dbi_writel(pcie, 0, PCIE_CS2_OFFSET + PCI_ROM_ADDRESS1); in ls_pcie_disable_bars()
331 static void ls_pcie_setup_ctrl(struct ls_pcie *pcie) in ls_pcie_setup_ctrl() argument
333 ls_pcie_setup_atu(pcie); in ls_pcie_setup_ctrl()
335 dbi_writel(pcie, 1, PCIE_DBI_RO_WR_EN); in ls_pcie_setup_ctrl()
336 ls_pcie_fix_class(pcie); in ls_pcie_setup_ctrl()
337 ls_pcie_clear_multifunction(pcie); in ls_pcie_setup_ctrl()
338 ls_pcie_drop_msg_tlp(pcie); in ls_pcie_setup_ctrl()
339 dbi_writel(pcie, 0, PCIE_DBI_RO_WR_EN); in ls_pcie_setup_ctrl()
341 ls_pcie_disable_bars(pcie); in ls_pcie_setup_ctrl()
344 static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie) in ls_pcie_ep_setup_atu() argument
349 ls_pcie_atu_inbound_set(pcie, 0, 0, phys); in ls_pcie_ep_setup_atu()
352 ls_pcie_atu_inbound_set(pcie, 1, 1, phys); in ls_pcie_ep_setup_atu()
353 /* ATU 2 : INBOUND : map BAR2 */ in ls_pcie_ep_setup_atu()
355 ls_pcie_atu_inbound_set(pcie, 2, 2, phys); in ls_pcie_ep_setup_atu()
358 ls_pcie_atu_inbound_set(pcie, 3, 4, phys); in ls_pcie_ep_setup_atu()
361 ls_pcie_atu_outbound_set(pcie, 0, in ls_pcie_ep_setup_atu()
363 pcie->cfg_res.start, in ls_pcie_ep_setup_atu()
377 writel(size - 1, bar_base + PCI_BASE_ADDRESS_0); in ls_pcie_ep_setup_bar()
380 writel(size - 1, bar_base + PCI_BASE_ADDRESS_1); in ls_pcie_ep_setup_bar()
382 case 2: in ls_pcie_ep_setup_bar()
383 writel(size - 1, bar_base + PCI_BASE_ADDRESS_2); in ls_pcie_ep_setup_bar()
387 writel(size - 1, bar_base + PCI_BASE_ADDRESS_4); in ls_pcie_ep_setup_bar()
397 /* BAR0 - 32bit - 4K configuration */ in ls_pcie_ep_setup_bars()
399 /* BAR1 - 32bit - 8K MSIX*/ in ls_pcie_ep_setup_bars()
401 /* BAR2 - 64bit - 4K MEM desciptor */ in ls_pcie_ep_setup_bars()
402 ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE); in ls_pcie_ep_setup_bars()
403 /* BAR4 - 64bit - 1M MEM*/ in ls_pcie_ep_setup_bars()
407 static void ls_pcie_ep_enable_cfg(struct ls_pcie *pcie) in ls_pcie_ep_enable_cfg() argument
409 ctrl_writel(pcie, PCIE_CONFIG_READY, PCIE_PF_CONFIG); in ls_pcie_ep_enable_cfg()
412 static void ls_pcie_setup_ep(struct ls_pcie *pcie) in ls_pcie_setup_ep() argument
416 sriov = readl(pcie->dbi + PCIE_SRIOV); in ls_pcie_setup_ep()
422 ctrl_writel(pcie, PCIE_LCTRL0_VAL(pf, vf), in ls_pcie_setup_ep()
425 ls_pcie_ep_setup_bars(pcie->dbi); in ls_pcie_setup_ep()
426 ls_pcie_ep_setup_atu(pcie); in ls_pcie_setup_ep()
430 ctrl_writel(pcie, 0, PCIE_PF_VF_CTRL); in ls_pcie_setup_ep()
432 ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE); in ls_pcie_setup_ep()
433 ls_pcie_ep_setup_atu(pcie); in ls_pcie_setup_ep()
436 ls_pcie_ep_enable_cfg(pcie); in ls_pcie_setup_ep()
441 struct ls_pcie *pcie = dev_get_priv(dev); in ls_pcie_probe() local
442 const void *fdt = gd->fdt_blob; in ls_pcie_probe()
449 pcie->bus = dev; in ls_pcie_probe()
451 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", in ls_pcie_probe()
452 "dbi", &pcie->dbi_res); in ls_pcie_probe()
454 printf("ls-pcie: resource \"dbi\" not found\n"); in ls_pcie_probe()
458 pcie->idx = (pcie->dbi_res.start - PCIE_SYS_BASE_ADDR) / PCIE_CCSR_SIZE; in ls_pcie_probe()
460 list_add(&pcie->list, &ls_pcie_list); in ls_pcie_probe()
462 pcie->enabled = is_serdes_configured(PCIE_SRDS_PRTCL(pcie->idx)); in ls_pcie_probe()
463 if (!pcie->enabled) { in ls_pcie_probe()
464 printf("PCIe%d: %s disabled\n", pcie->idx, dev->name); in ls_pcie_probe()
468 pcie->dbi = map_physmem(pcie->dbi_res.start, in ls_pcie_probe()
469 fdt_resource_size(&pcie->dbi_res), in ls_pcie_probe()
472 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", in ls_pcie_probe()
473 "lut", &pcie->lut_res); in ls_pcie_probe()
475 pcie->lut = map_physmem(pcie->lut_res.start, in ls_pcie_probe()
476 fdt_resource_size(&pcie->lut_res), in ls_pcie_probe()
479 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", in ls_pcie_probe()
480 "ctrl", &pcie->ctrl_res); in ls_pcie_probe()
482 pcie->ctrl = map_physmem(pcie->ctrl_res.start, in ls_pcie_probe()
483 fdt_resource_size(&pcie->ctrl_res), in ls_pcie_probe()
485 if (!pcie->ctrl) in ls_pcie_probe()
486 pcie->ctrl = pcie->lut; in ls_pcie_probe()
488 if (!pcie->ctrl) { in ls_pcie_probe()
489 printf("%s: NOT find CTRL\n", dev->name); in ls_pcie_probe()
490 return -1; in ls_pcie_probe()
493 ret = fdt_get_named_resource(fdt, node, "reg", "reg-names", in ls_pcie_probe()
494 "config", &pcie->cfg_res); in ls_pcie_probe()
496 printf("%s: resource \"config\" not found\n", dev->name); in ls_pcie_probe()
501 * Fix the pcie memory map address and PF control registers address in ls_pcie_probe()
509 cfg_size = fdt_resource_size(&pcie->cfg_res); in ls_pcie_probe()
510 pcie->cfg_res.start = LS2088A_PCIE1_PHYS_ADDR + in ls_pcie_probe()
511 LS2088A_PCIE_PHYS_SIZE * pcie->idx; in ls_pcie_probe()
512 pcie->cfg_res.end = pcie->cfg_res.start + cfg_size; in ls_pcie_probe()
513 pcie->ctrl = pcie->lut + 0x40000; in ls_pcie_probe()
516 pcie->cfg0 = map_physmem(pcie->cfg_res.start, in ls_pcie_probe()
517 fdt_resource_size(&pcie->cfg_res), in ls_pcie_probe()
519 pcie->cfg1 = pcie->cfg0 + fdt_resource_size(&pcie->cfg_res) / 2; in ls_pcie_probe()
521 pcie->big_endian = fdtdec_get_bool(fdt, node, "big-endian"); in ls_pcie_probe()
523 debug("%s dbi:%lx lut:%lx ctrl:0x%lx cfg0:0x%lx, big-endian:%d\n", in ls_pcie_probe()
524 dev->name, (unsigned long)pcie->dbi, (unsigned long)pcie->lut, in ls_pcie_probe()
525 (unsigned long)pcie->ctrl, (unsigned long)pcie->cfg0, in ls_pcie_probe()
526 pcie->big_endian); in ls_pcie_probe()
528 pcie->mode = readb(pcie->dbi + PCI_HEADER_TYPE) & 0x7f; in ls_pcie_probe()
530 if (pcie->mode == PCI_HEADER_TYPE_NORMAL) { in ls_pcie_probe()
531 printf("PCIe%u: %s %s", pcie->idx, dev->name, "Endpoint"); in ls_pcie_probe()
532 ls_pcie_setup_ep(pcie); in ls_pcie_probe()
534 printf("PCIe%u: %s %s", pcie->idx, dev->name, "Root Complex"); in ls_pcie_probe()
535 ls_pcie_setup_ctrl(pcie); in ls_pcie_probe()
538 if (!ls_pcie_link_up(pcie)) { in ls_pcie_probe()
539 /* Let the user know there's no PCIe link */ in ls_pcie_probe()
544 /* Print the negotiated PCIe link width */ in ls_pcie_probe()
545 link_sta = readw(pcie->dbi + PCIE_LINK_STA); in ls_pcie_probe()
558 { .compatible = "fsl,ls-pcie" },