Lines Matching full:pcie
3 * Intel FPGA PCIe host controller driver
37 #define RP_CFG_ADDR(pcie, reg) \ argument
38 ((pcie->hip_base) + (reg) + (1 << 20))
41 #define TLP_CFGRD_DW0(pcie, bus) \ argument
42 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0 \
46 #define TLP_CFGWR_DW0(pcie, bus) \ argument
47 ((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0 \
51 #define TLP_CFG_DW1(pcie, tag, be) \ argument
52 (((TLP_REQ_ID(pcie->first_busno, RP_DEVFN)) << 16) | (tag << 8) | (be))
62 #define IS_ROOT_PORT(pcie, bdf) \ argument
63 ((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
69 * struct intel_fpga_pcie - Intel FPGA PCIe controller state
73 * @first_busno: This driver supports multiple PCIe controllers.
74 * first_busno stores the bus number of the PCIe root-port
75 * number which may vary depending on the PCIe setup.
85 * Intel FPGA PCIe port uses BAR0 of RC's configuration space as the
87 * into PCIe space using these registers, so it can be reached by DMA from
90 * sizing and resource allocation by PCIe core.
92 static bool intel_fpga_pcie_hide_rc_bar(struct intel_fpga_pcie *pcie, in intel_fpga_pcie_hide_rc_bar() argument
95 if (IS_ROOT_PORT(pcie, bdf) && PCI_DEV(bdf) == 0 && in intel_fpga_pcie_hide_rc_bar()
102 static inline void cra_writel(struct intel_fpga_pcie *pcie, const u32 value, in cra_writel() argument
105 writel(value, pcie->cra_base + reg); in cra_writel()
108 static inline u32 cra_readl(struct intel_fpga_pcie *pcie, const u32 reg) in cra_readl() argument
110 return readl(pcie->cra_base + reg); in cra_readl()
113 static bool intel_fpga_pcie_link_up(struct intel_fpga_pcie *pcie) in intel_fpga_pcie_link_up() argument
115 return !!(readw(RP_CFG_ADDR(pcie, RP_CAP_OFFSET + PCI_EXP_LNKSTA)) in intel_fpga_pcie_link_up()
119 static bool intel_fpga_pcie_addr_valid(struct intel_fpga_pcie *pcie, in intel_fpga_pcie_addr_valid() argument
123 if (!IS_ROOT_PORT(pcie, bdf) && !intel_fpga_pcie_link_up(pcie)) in intel_fpga_pcie_addr_valid()
127 if (IS_ROOT_PORT(pcie, bdf) && PCI_DEV(bdf) > 0) in intel_fpga_pcie_addr_valid()
130 if ((PCI_BUS(bdf) == pcie->first_busno + 1) && PCI_DEV(bdf) > 0) in intel_fpga_pcie_addr_valid()
136 static void tlp_write_tx(struct intel_fpga_pcie *pcie, u32 reg0, u32 ctrl) in tlp_write_tx() argument
138 cra_writel(pcie, reg0, RP_TX_REG0); in tlp_write_tx()
139 cra_writel(pcie, ctrl, RP_TX_CNTRL); in tlp_write_tx()
142 static int tlp_read_packet(struct intel_fpga_pcie *pcie, u32 *value) in tlp_read_packet() argument
151 ctrl = cra_readl(pcie, RP_RXCPL_STATUS); in tlp_read_packet()
156 dw[count++] = cra_readl(pcie, RP_RXCPL_REG); in tlp_read_packet()
160 ctrl = cra_readl(pcie, RP_RXCPL_STATUS); in tlp_read_packet()
161 dw[count++] = cra_readl(pcie, RP_RXCPL_REG); in tlp_read_packet()
179 dev_err(pcie->dev, "read TLP packet timed out\n"); in tlp_read_packet()
183 static void tlp_write_packet(struct intel_fpga_pcie *pcie, u32 *headers, in tlp_write_packet() argument
186 tlp_write_tx(pcie, headers[0], RP_TX_SOP); in tlp_write_packet()
188 tlp_write_tx(pcie, headers[1], 0); in tlp_write_packet()
190 tlp_write_tx(pcie, headers[2], 0); in tlp_write_packet()
192 tlp_write_tx(pcie, data, RP_TX_EOP); in tlp_write_packet()
195 static int tlp_cfg_dword_read(struct intel_fpga_pcie *pcie, pci_dev_t bdf, in tlp_cfg_dword_read() argument
201 headers[0] = TLP_CFGRD_DW0(pcie, busno); in tlp_cfg_dword_read()
202 headers[1] = TLP_CFG_DW1(pcie, TLP_READ_TAG, byte_en); in tlp_cfg_dword_read()
205 tlp_write_packet(pcie, headers, 0); in tlp_cfg_dword_read()
207 return tlp_read_packet(pcie, value); in tlp_cfg_dword_read()
210 static int tlp_cfg_dword_write(struct intel_fpga_pcie *pcie, pci_dev_t bdf, in tlp_cfg_dword_write() argument
216 headers[0] = TLP_CFGWR_DW0(pcie, busno); in tlp_cfg_dword_write()
217 headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en); in tlp_cfg_dword_write()
220 tlp_write_packet(pcie, headers, value); in tlp_cfg_dword_write()
222 return tlp_read_packet(pcie, NULL); in tlp_cfg_dword_write()
228 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_rp_conf_addr() local
230 *paddress = RP_CFG_ADDR(pcie, offset); in intel_fpga_rp_conf_addr()
248 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in intel_fpga_pcie_rp_wr_conf() local
257 pcie->first_busno = (u8)(value); in intel_fpga_pcie_rp_wr_conf()
275 static int _pcie_intel_fpga_read_config(struct intel_fpga_pcie *pcie, in _pcie_intel_fpga_read_config() argument
284 if (IS_ROOT_PORT(pcie, bdf)) in _pcie_intel_fpga_read_config()
285 return intel_fpga_pcie_rp_rd_conf(pcie->bus, bdf, in _pcie_intel_fpga_read_config()
289 ret = tlp_cfg_dword_read(pcie, bdf, offset & ~DWORD_MASK, in _pcie_intel_fpga_read_config()
294 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n", in _pcie_intel_fpga_read_config()
301 static int _pcie_intel_fpga_write_config(struct intel_fpga_pcie *pcie, in _pcie_intel_fpga_write_config() argument
308 dev_dbg(pcie->dev, "PCIE CFG write: (b.d.f)=(%02d.%02d.%02d)\n", in _pcie_intel_fpga_write_config()
310 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", in _pcie_intel_fpga_write_config()
314 if (IS_ROOT_PORT(pcie, bdf)) in _pcie_intel_fpga_write_config()
315 return intel_fpga_pcie_rp_wr_conf(pcie->bus, bdf, offset, in _pcie_intel_fpga_write_config()
321 return tlp_cfg_dword_write(pcie, bdf, offset & ~DWORD_MASK, in _pcie_intel_fpga_write_config()
329 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_read_config() local
331 dev_dbg(pcie->dev, "PCIE CFG read: (b.d.f)=(%02d.%02d.%02d)\n", in pcie_intel_fpga_read_config()
334 if (intel_fpga_pcie_hide_rc_bar(pcie, bdf, offset)) { in pcie_intel_fpga_read_config()
339 if (!intel_fpga_pcie_addr_valid(pcie, bdf)) { in pcie_intel_fpga_read_config()
344 return _pcie_intel_fpga_read_config(pcie, bdf, offset, valuep, size); in pcie_intel_fpga_read_config()
351 struct intel_fpga_pcie *pcie = dev_get_priv(bus); in pcie_intel_fpga_write_config() local
353 if (intel_fpga_pcie_hide_rc_bar(pcie, bdf, offset)) in pcie_intel_fpga_write_config()
356 if (!intel_fpga_pcie_addr_valid(pcie, bdf)) in pcie_intel_fpga_write_config()
359 return _pcie_intel_fpga_write_config(pcie, bdf, offset, value, in pcie_intel_fpga_write_config()
365 struct intel_fpga_pcie *pcie = dev_get_priv(dev); in pcie_intel_fpga_probe() local
367 pcie->bus = pci_get_controller(dev); in pcie_intel_fpga_probe()
368 pcie->first_busno = dev->seq; in pcie_intel_fpga_probe()
371 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS); in pcie_intel_fpga_probe()
373 cra_writel(pcie, 0, P2A_INT_ENABLE); in pcie_intel_fpga_probe()
380 struct intel_fpga_pcie *pcie = dev_get_priv(dev); in pcie_intel_fpga_ofdata_to_platdata() local
394 pcie->cra_base = map_physmem(reg_res.start, in pcie_intel_fpga_ofdata_to_platdata()
405 pcie->hip_base = map_physmem(reg_res.start, in pcie_intel_fpga_ofdata_to_platdata()
418 { .compatible = "altr,pcie-root-port-2.0" },