drivers/pci/pcie_intel_fpga.c

1 // SPDX-License-Identifier: GPL-2.0
3  * Intel FPGA PCIe host controller driver
5  * Copyright (C) 2013-2018 Intel Corporation. All rights reserved
38 		((pcie->hip_base) + (reg) + (1 << 20))
42 	((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGRD0		\
47 	((((bus != pcie->first_busno) ? TLP_FMTTYPE_CFGWR0		\
52 	(((TLP_REQ_ID(pcie->first_busno,  RP_DEVFN)) << 16) | (tag << 8) | (be))
63 		((PCI_BUS(bdf) == pcie->first_busno) ? true : false)
69  * struct intel_fpga_pcie - Intel FPGA PCIe controller state
74  *               first_busno stores the bus number of the PCIe root-port
85  * Intel FPGA PCIe port uses BAR0 of RC's configuration space as the
89  * The BAR0 of bridge should be hidden during enumeration to avoid the
105 	writel(value, pcie->cra_base + reg);  in cra_writel()
110 	return readl(pcie->cra_base + reg);  in cra_readl()
130 	if ((PCI_BUS(bdf) == pcie->first_busno + 1) && PCI_DEV(bdf) > 0)  in intel_fpga_pcie_addr_valid()
165 					return -EFAULT;  in tlp_read_packet()
179 	dev_err(pcie->dev, "read TLP packet timed out\n");  in tlp_read_packet()
180 	return -ENODEV;  in tlp_read_packet()
257 			pcie->first_busno = (u8)(value);  in intel_fpga_pcie_rp_wr_conf()
285 		return intel_fpga_pcie_rp_rd_conf(pcie->bus, bdf,  in _pcie_intel_fpga_read_config()
294 	dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",  in _pcie_intel_fpga_read_config()
308 	dev_dbg(pcie->dev, "PCIE CFG write: (b.d.f)=(%02d.%02d.%02d)\n",  in _pcie_intel_fpga_write_config()
310 	dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",  in _pcie_intel_fpga_write_config()
315 		return intel_fpga_pcie_rp_wr_conf(pcie->bus, bdf, offset,  in _pcie_intel_fpga_write_config()
331 	dev_dbg(pcie->dev, "PCIE CFG read:  (b.d.f)=(%02d.%02d.%02d)\n",  in pcie_intel_fpga_read_config()
367 	pcie->bus = pci_get_controller(dev);  in pcie_intel_fpga_probe()
368 	pcie->first_busno = dev->seq;  in pcie_intel_fpga_probe()
387 	ret = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names",  in pcie_intel_fpga_ofdata_to_platdata()
394 	pcie->cra_base = map_physmem(reg_res.start,  in pcie_intel_fpga_ofdata_to_platdata()
398 	ret = fdt_get_named_resource(gd->fdt_blob, node, "reg", "reg-names",  in pcie_intel_fpga_ofdata_to_platdata()
405 	pcie->hip_base = map_physmem(reg_res.start,  in pcie_intel_fpga_ofdata_to_platdata()
418 	{ .compatible = "altr,pcie-root-port-2.0" },