21 	u32 timeout = 0;  in aspeed_pcie_set_slot_power_limit()
26 	case 0:  in aspeed_pcie_set_slot_power_limit()
36 	txTag %= 0x7;  in aspeed_pcie_set_slot_power_limit()
38 	writel(0x74000001, &h2x_reg->h2x_tx_desc3);  in aspeed_pcie_set_slot_power_limit()
40 	case 0:	//write for 0.8.0  in aspeed_pcie_set_slot_power_limit()
41 		writel(0x00400050 | (txTag << 8), &h2x_reg->h2x_tx_desc2);  in aspeed_pcie_set_slot_power_limit()
43 	case 1:	//write for 0.4.0  in aspeed_pcie_set_slot_power_limit()
44 		writel(0x00200050 | (txTag << 8), &h2x_reg->h2x_tx_desc2);  in aspeed_pcie_set_slot_power_limit()
47 	writel(0x0, &h2x_reg->h2x_tx_desc1);  in aspeed_pcie_set_slot_power_limit()
48 	writel(0x0, &h2x_reg->h2x_tx_desc0);  in aspeed_pcie_set_slot_power_limit()
50 	writel(0x1a, &h2x_reg->h2x_tx_data);  in aspeed_pcie_set_slot_power_limit()
64 	timeout = 0;  in aspeed_pcie_set_slot_power_limit()
67 	case 0:  in aspeed_pcie_set_slot_power_limit()
96 	u32 timeout = 0;  in aspeed_pcie_cfg_read()
98 	u32 type = 0;  in aspeed_pcie_cfg_read()
99 	int rx_done_fail = 0;  in aspeed_pcie_cfg_read()
108 	if (PCI_BUS(bdf) == 0)  in aspeed_pcie_cfg_read()
109 		type = 0;  in aspeed_pcie_cfg_read()
118 	txTag %= 0x7;  in aspeed_pcie_cfg_read()
120 	writel(0x04000001 | (type << 24), &h2x_reg->h2x_tx_desc3);  in aspeed_pcie_cfg_read()
121 	writel(0x0000200f | (txTag << 8), &h2x_reg->h2x_tx_desc2);  in aspeed_pcie_cfg_read()
123 	writel(0x00000000, &h2x_reg->h2x_tx_desc0);  in aspeed_pcie_cfg_read()
132 			*valuep = 0xffffffff;  in aspeed_pcie_cfg_read()
140 	timeout = 0;  in aspeed_pcie_cfg_read()
148 				*valuep = 0xffffffff;  in aspeed_pcie_cfg_read()
155 				*valuep = 0xffffffff;  in aspeed_pcie_cfg_read()
169 				*valuep = 0xffffffff;  in aspeed_pcie_cfg_read()
176 				*valuep = 0xffffffff;  in aspeed_pcie_cfg_read()
198 	u32 timeout = 0;  in aspeed_pcie_cfg_write()
199 	u32 type = 0;  in aspeed_pcie_cfg_write()
201 	u8 byte_en = 0;  in aspeed_pcie_cfg_write()
211 		case 0:  in aspeed_pcie_cfg_write()
212 			byte_en = 0x1;  in aspeed_pcie_cfg_write()
215 			byte_en = 0x2;  in aspeed_pcie_cfg_write()
218 			byte_en = 0x4;  in aspeed_pcie_cfg_write()
221 			byte_en = 0x8;  in aspeed_pcie_cfg_write()
227 		case 0:  in aspeed_pcie_cfg_write()
228 			byte_en = 0x3;  in aspeed_pcie_cfg_write()
231 			byte_en = 0xc;  in aspeed_pcie_cfg_write()
236 		byte_en = 0xf;  in aspeed_pcie_cfg_write()
240 	if (PCI_BUS(bdf) == 0)  in aspeed_pcie_cfg_write()
241 		type = 0;  in aspeed_pcie_cfg_write()
250 	txTag %= 0x7;  in aspeed_pcie_cfg_write()
252 	writel(0x44000001 | (type << 24), &h2x_reg->h2x_tx_desc3);  in aspeed_pcie_cfg_write()
253 	writel(0x00002000 | (txTag << 8) | byte_en, &h2x_reg->h2x_tx_desc2);  in aspeed_pcie_cfg_write()
255 	writel(0x00000000, &h2x_reg->h2x_tx_desc0);  in aspeed_pcie_cfg_write()
257 	value = pci_conv_size_to_32(0x0, value, offset, size);  in aspeed_pcie_cfg_write()
274 	timeout = 0;  in aspeed_pcie_cfg_write()
311 	if (PCI_BUS(bdf) == 1 && PCI_DEV(bdf) > 0) {  in pcie_aspeed_read_config()
314 		 * If local dev is 0, the first other dev can  in pcie_aspeed_read_config()
318 		return 0;  in pcie_aspeed_read_config()
321 	if (PCI_BUS(bdf) == 2 && PCI_DEV(bdf) > 0) {  in pcie_aspeed_read_config()
324 		 * If local dev is 0, the first other dev can  in pcie_aspeed_read_config()
328 		return 0;  in pcie_aspeed_read_config()
334 	debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, *valuep);  in pcie_aspeed_read_config()
336 	return 0;  in pcie_aspeed_read_config()
347 	debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);  in pcie_aspeed_write_config()
351 	return 0;  in pcie_aspeed_write_config()
360 	case 0:  in aspeed_pcie_rc_slot_enable()
389 	int ret = 0;  in pcie_aspeed_probe()
391 	txTag = 0;  in pcie_aspeed_probe()
392 	ret = reset_get_by_index(dev, 0, &reset_ctl);  in pcie_aspeed_probe()
403 	writel(0x34000000, &h2x_reg->h2x_tx_desc3);  in pcie_aspeed_probe()
404 	writel(0x0000007f, &h2x_reg->h2x_tx_desc2);  in pcie_aspeed_probe()
405 	writel(0x00001a03, &h2x_reg->h2x_tx_desc1);  in pcie_aspeed_probe()
406 	writel(0x00000000, &h2x_reg->h2x_tx_desc0);  in pcie_aspeed_probe()
417 	writel(0xe0006000, &h2x_reg->h2x_reg60);  in pcie_aspeed_probe()
418 	writel(0x0, &h2x_reg->h2x_reg64);  in pcie_aspeed_probe()
419 	writel(0xFFFFFFFF, &h2x_reg->h2x_reg68);  in pcie_aspeed_probe()
422 	writel(BIT(0), &h2x_reg->h2x_reg00);  in pcie_aspeed_probe()
432 		aspeed_pcie_rc_slot_enable(pcie, 0);  in pcie_aspeed_probe()
439 			aspeed_pcie_set_slot_power_limit(pcie, 0);  in pcie_aspeed_probe()
461 	return 0;  in pcie_aspeed_probe()
469 	pcie->h2x_reg = (void *)devfdt_get_addr_index(dev, 0);  in pcie_aspeed_ofdata_to_platdata()
471 	return 0;  in pcie_aspeed_ofdata_to_platdata()