Lines Matching +full:pcie +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0
6 * Based on NVIDIA PCIe driver
7 * Copyright (c) 2008-2009, NVIDIA Corporation.
9 * Copyright (c) 2013-2014, NVIDIA Corporation.
12 #define pr_fmt(fmt) "tegra-pcie: " fmt
21 #include <power-domain.h>
33 #include <asm/arch-tegra/xusb-padctl.h>
34 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
41 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be
88 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
98 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
122 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
163 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
164 * entries, one entry per PCIe port. These field definitions and desired
167 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
195 struct tegra_pcie *pcie; member
240 static void afi_writel(struct tegra_pcie *pcie, unsigned long value, in afi_writel() argument
243 writel(value, pcie->afi.start + offset); in afi_writel()
246 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset) in afi_readl() argument
248 return readl(pcie->afi.start + offset); in afi_readl()
251 static void pads_writel(struct tegra_pcie *pcie, unsigned long value, in pads_writel() argument
254 writel(value, pcie->pads.start + offset); in pads_writel()
258 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset) in pads_readl() argument
260 return readl(pcie->pads.start + offset); in pads_readl()
267 return readl(port->regs.start + offset); in rp_readl()
273 writel(value, port->regs.start + offset); in rp_writel()
283 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf, in tegra_pcie_conf_address() argument
292 list_for_each_entry(port, &pcie->ports, list) { in tegra_pcie_conf_address()
293 if (port->index + 1 == dev) { in tegra_pcie_conf_address()
294 *address = port->regs.start + (where & ~3); in tegra_pcie_conf_address()
298 return -EFAULT; in tegra_pcie_conf_address()
303 return -EFAULT; in tegra_pcie_conf_address()
306 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where); in tegra_pcie_conf_address()
315 struct tegra_pcie *pcie = dev_get_priv(bus); in pci_tegra_read_config() local
319 err = tegra_pcie_conf_address(pcie, bdf, offset, &address); in pci_tegra_read_config()
347 struct tegra_pcie *pcie = dev_get_priv(bus); in pci_tegra_write_config() local
352 err = tegra_pcie_conf_address(pcie, bdf, offset, &address); in pci_tegra_write_config()
368 addr = ofnode_get_property(node, "assigned-addresses", &len); in tegra_pcie_port_parse_dt()
370 pr_err("property \"assigned-addresses\" not found"); in tegra_pcie_port_parse_dt()
371 return -FDT_ERR_NOTFOUND; in tegra_pcie_port_parse_dt()
374 port->regs.start = fdt32_to_cpu(addr[2]); in tegra_pcie_port_parse_dt()
375 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]); in tegra_pcie_port_parse_dt()
387 debug("single-mode configuration\n"); in tegra_pcie_get_xbar_config()
392 debug("dual-mode configuration\n"); in tegra_pcie_get_xbar_config()
400 debug("4x1, 2x1 configuration\n"); in tegra_pcie_get_xbar_config()
405 debug("2x3 configuration\n"); in tegra_pcie_get_xbar_config()
424 debug("2x1, 1x1 configuration\n"); in tegra_pcie_get_xbar_config()
451 return -FDT_ERR_NOTFOUND; in tegra_pcie_get_xbar_config()
459 err = ofnode_read_u32_default(node, "nvidia,num-lanes", -1); in tegra_pcie_parse_port_info()
461 pr_err("failed to parse \"nvidia,num-lanes\" property"); in tegra_pcie_parse_port_info()
473 *index = PCI_DEV(addr.phys_hi) - 1; in tegra_pcie_parse_port_info()
484 struct tegra_pcie *pcie) in tegra_pcie_parse_dt() argument
490 err = dev_read_resource(dev, 0, &pcie->pads); in tegra_pcie_parse_dt()
496 err = dev_read_resource(dev, 1, &pcie->afi); in tegra_pcie_parse_dt()
502 err = dev_read_resource(dev, 2, &pcie->cs); in tegra_pcie_parse_dt()
515 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE); in tegra_pcie_parse_dt()
516 if (pcie->phy) { in tegra_pcie_parse_dt()
517 err = tegra_xusb_phy_prepare(pcie->phy); in tegra_pcie_parse_dt()
545 port->num_lanes = num_lanes; in tegra_pcie_parse_dt()
546 port->index = index; in tegra_pcie_parse_dt()
554 list_add_tail(&port->list, &pcie->ports); in tegra_pcie_parse_dt()
555 port->pcie = pcie; in tegra_pcie_parse_dt()
559 &pcie->xbar); in tegra_pcie_parse_dt()
569 static int tegra_pcie_power_on(struct tegra_pcie *pcie) in tegra_pcie_power_on() argument
573 ret = power_domain_on(&pcie->pwrdom); in tegra_pcie_power_on()
579 ret = clk_enable(&pcie->clk_afi); in tegra_pcie_power_on()
585 ret = clk_enable(&pcie->clk_pex); in tegra_pcie_power_on()
591 ret = reset_deassert(&pcie->reset_afi); in tegra_pcie_power_on()
597 ret = reset_deassert(&pcie->reset_pex); in tegra_pcie_power_on()
606 static int tegra_pcie_power_on(struct tegra_pcie *pcie) in tegra_pcie_power_on() argument
608 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_power_on()
612 /* reset PCIEXCLK logic, AFI controller and PCIe controller */ in tegra_pcie_power_on()
619 pr_err("failed to power off PCIe partition: %d", err); in tegra_pcie_power_on()
626 pr_err("failed to power up PCIe partition: %d", err); in tegra_pcie_power_on()
636 if (soc->has_cml_clk) { in tegra_pcie_power_on()
653 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout) in tegra_pcie_pll_wait() argument
655 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_pll_wait()
660 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_pll_wait()
665 return -ETIMEDOUT; in tegra_pcie_pll_wait()
668 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie) in tegra_pcie_phy_enable() argument
670 const struct tegra_pcie_soc *soc = pcie->soc; in tegra_pcie_phy_enable()
674 /* initialize internal PHY, enable up to 16 PCIe lanes */ in tegra_pcie_phy_enable()
675 pads_writel(pcie, 0, PADS_CTL_SEL); in tegra_pcie_phy_enable()
678 value = pads_readl(pcie, PADS_CTL); in tegra_pcie_phy_enable()
680 pads_writel(pcie, value, PADS_CTL); in tegra_pcie_phy_enable()
686 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
688 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel; in tegra_pcie_phy_enable()
689 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
692 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
694 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
699 value = pads_readl(pcie, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
701 pads_writel(pcie, value, soc->pads_pll_ctl); in tegra_pcie_phy_enable()
704 err = tegra_pcie_pll_wait(pcie, 500); in tegra_pcie_phy_enable()
711 value = pads_readl(pcie, PADS_CTL); in tegra_pcie_phy_enable()
713 pads_writel(pcie, value, PADS_CTL); in tegra_pcie_phy_enable()
716 value = pads_readl(pcie, PADS_CTL); in tegra_pcie_phy_enable()
718 pads_writel(pcie, value, PADS_CTL); in tegra_pcie_phy_enable()
724 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie) argument
726 const struct tegra_pcie_soc *soc = pcie->soc;
734 if (pcie->phy) {
736 value = afi_readl(pcie, AFI_PLLE_CONTROL);
739 afi_writel(pcie, value, AFI_PLLE_CONTROL);
742 if (soc->has_pex_bias_ctrl)
743 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
745 value = afi_readl(pcie, AFI_PCIE_CONFIG);
747 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar;
749 list_for_each_entry(port, &pcie->ports, list)
750 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
752 afi_writel(pcie, value, AFI_PCIE_CONFIG);
754 value = afi_readl(pcie, AFI_FUSE);
756 if (soc->has_gen2)
761 afi_writel(pcie, value, AFI_FUSE);
764 if (pcie->phy)
765 err = tegra_xusb_phy_enable(pcie->phy);
767 err = tegra_pcie_phy_enable(pcie);
777 err = reset_deassert(&pcie->reset_pcie_x);
786 /* finally enable PCIe */
787 value = afi_readl(pcie, AFI_CONFIGURATION);
789 afi_writel(pcie, value, AFI_CONFIGURATION);
792 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE);
793 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE);
794 afi_writel(pcie, 0, AFI_INTR_MASK);
795 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
802 struct tegra_pcie *pcie = dev_get_priv(bus); local
809 size = resource_size(&pcie->cs);
810 axi = pcie->cs.start;
812 afi_writel(pcie, axi, AFI_AXI_BAR0_START);
813 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
814 afi_writel(pcie, fpci, AFI_FPCI_BAR0);
818 return -EINVAL;
822 size = io->size;
823 axi = io->phys_start;
825 afi_writel(pcie, axi, AFI_AXI_BAR1_START);
826 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
827 afi_writel(pcie, fpci, AFI_FPCI_BAR1);
829 /* BAR 2: prefetchable memory */
830 fpci = (((pref->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
831 size = pref->size;
832 axi = pref->phys_start;
834 afi_writel(pcie, axi, AFI_AXI_BAR2_START);
835 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
836 afi_writel(pcie, fpci, AFI_FPCI_BAR2);
838 /* BAR 3: non-prefetchable memory */
839 fpci = (((mem->phys_start >> 12) & 0x0fffffff) << 4) | 0x1;
840 size = mem->size;
841 axi = mem->phys_start;
843 afi_writel(pcie, axi, AFI_AXI_BAR3_START);
844 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
845 afi_writel(pcie, fpci, AFI_FPCI_BAR3);
848 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
849 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
850 afi_writel(pcie, 0, AFI_FPCI_BAR4);
852 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
853 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
854 afi_writel(pcie, 0, AFI_FPCI_BAR5);
857 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST);
858 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
859 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
860 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
863 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
864 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
865 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
866 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
875 switch (port->index) {
884 case 2:
885 ret = port->pcie->soc->afi_pex2_ctrl;
898 value = afi_readl(port->pcie, ctrl);
900 afi_writel(port->pcie, value, ctrl);
904 value = afi_readl(port->pcie, ctrl);
906 afi_writel(port->pcie, value, ctrl);
911 return port->index;
921 struct tegra_pcie *pcie = port->pcie; local
922 const struct tegra_pcie_soc *soc = pcie->soc;
927 value = afi_readl(pcie, ctrl);
930 if (pcie->soc->has_pex_clkreq_en)
935 afi_writel(pcie, value, ctrl);
939 if (soc->force_pca_enable) {
946 pads_writel(pcie, soc->pads_refclk_cfg0, PADS_REFCLK_CFG0);
947 if (soc->num_ports > 2)
948 pads_writel(pcie, soc->pads_refclk_cfg1, PADS_REFCLK_CFG1);
970 } while (--timeout);
973 debug("link %u down, retrying\n", port->index);
985 } while (--timeout);
989 } while (--retries);
1000 value = afi_readl(port->pcie, ctrl);
1002 afi_writel(port->pcie, value, ctrl);
1005 value = afi_readl(port->pcie, ctrl);
1007 afi_writel(port->pcie, value, ctrl);
1012 list_del(&port->list);
1016 static int tegra_pcie_enable(struct tegra_pcie *pcie) argument
1020 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
1021 debug("probing port %u, using %u lanes\n", port->index,
1022 port->num_lanes);
1029 debug("link %u down, ignoring\n", port->index);
1040 .num_ports = 2,
1062 .num_ports = 2,
1072 .num_ports = 2,
1095 struct tegra_pcie *pcie = dev_get_priv(dev); local
1099 pcie->soc = &pci_tegra_soc[id];
1101 INIT_LIST_HEAD(&pcie->ports);
1103 if (tegra_pcie_parse_dt(dev, id, pcie))
1104 return -EINVAL;
1111 struct tegra_pcie *pcie = dev_get_priv(dev); local
1115 err = clk_get_by_name(dev, "afi", &pcie->clk_afi);
1121 err = clk_get_by_name(dev, "pex", &pcie->clk_pex);
1127 err = reset_get_by_name(dev, "afi", &pcie->reset_afi);
1133 err = reset_get_by_name(dev, "pex", &pcie->reset_pex);
1139 err = reset_get_by_name(dev, "pcie_x", &pcie->reset_pcie_x);
1145 err = power_domain_get(dev, &pcie->pwrdom);
1152 err = tegra_pcie_power_on(pcie);
1158 err = tegra_pcie_enable_controller(pcie);
1170 err = tegra_pcie_enable(pcie);
1172 pr_err("failed to enable PCIe");
1185 { .compatible = "nvidia,tegra20-pcie", .data = TEGRA20_PCIE },
1186 { .compatible = "nvidia,tegra30-pcie", .data = TEGRA30_PCIE },
1187 { .compatible = "nvidia,tegra124-pcie", .data = TEGRA124_PCIE },
1188 { .compatible = "nvidia,tegra210-pcie", .data = TEGRA210_PCIE },
1189 { .compatible = "nvidia,tegra186-pcie", .data = TEGRA186_PCIE },