20 void dm_pciauto_setup_device(struct udevice *dev, int bars_num,  in dm_pciauto_setup_device()  argument
36 	dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);  in dm_pciauto_setup_device()
44 			dm_pci_write_config32(dev, bar, 0xffffffff);  in dm_pciauto_setup_device()
45 		dm_pci_read_config32(dev, bar, &bar_response);  in dm_pciauto_setup_device()
69 					dm_pci_write_config32(dev, bar + 4,  in dm_pciauto_setup_device()
72 				dm_pci_read_config32(dev, bar + 4,  in dm_pciauto_setup_device()
104 			dm_pci_write_config32(dev, bar, (u32)bar_value);  in dm_pciauto_setup_device()
109 				dm_pci_write_config32(dev, bar,  in dm_pciauto_setup_device()
117 				dm_pci_write_config32(dev, bar, 0x00000000);  in dm_pciauto_setup_device()
131 		dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);  in dm_pciauto_setup_device()
136 			dm_pci_write_config32(dev, rom_addr, 0xfffffffe);  in dm_pciauto_setup_device()
137 			dm_pci_read_config32(dev, rom_addr, &bar_response);  in dm_pciauto_setup_device()
145 					dm_pci_write_config32(dev, rom_addr,  in dm_pciauto_setup_device()
155 	dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);  in dm_pciauto_setup_device()
159 	dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);  in dm_pciauto_setup_device()
160 	dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,  in dm_pciauto_setup_device()
162 	dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);  in dm_pciauto_setup_device()
165 void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)  in dm_pciauto_prescan_setup_bridge()  argument
171 	struct udevice *ctlr = pci_get_controller(dev);  in dm_pciauto_prescan_setup_bridge()
178 	dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);  in dm_pciauto_prescan_setup_bridge()
179 	dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);  in dm_pciauto_prescan_setup_bridge()
183 	dm_pci_write_config8(dev, PCI_PRIMARY_BUS,  in dm_pciauto_prescan_setup_bridge()
184 			     PCI_BUS(dm_pci_get_bdf(dev)) - ctlr->seq);  in dm_pciauto_prescan_setup_bridge()
185 	dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - ctlr->seq);  in dm_pciauto_prescan_setup_bridge()
186 	dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);  in dm_pciauto_prescan_setup_bridge()
196 		dm_pci_write_config16(dev, PCI_MEMORY_BASE,  in dm_pciauto_prescan_setup_bridge()
210 		dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,  in dm_pciauto_prescan_setup_bridge()
214 			dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,  in dm_pciauto_prescan_setup_bridge()
217 			dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);  in dm_pciauto_prescan_setup_bridge()
223 		dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);  in dm_pciauto_prescan_setup_bridge()
224 		dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);  in dm_pciauto_prescan_setup_bridge()
226 			dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);  in dm_pciauto_prescan_setup_bridge()
227 			dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);  in dm_pciauto_prescan_setup_bridge()
235 		dm_pci_write_config8(dev, PCI_IO_BASE,  in dm_pciauto_prescan_setup_bridge()
237 		dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,  in dm_pciauto_prescan_setup_bridge()
244 	dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);  in dm_pciauto_prescan_setup_bridge()
247 void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)  in dm_pciauto_postscan_setup_bridge()  argument
252 	struct udevice *ctlr = pci_get_controller(dev);  in dm_pciauto_postscan_setup_bridge()
254 	struct pci_child_platdata *pplat = dev_get_parent_platdata(dev);  in dm_pciauto_postscan_setup_bridge()
261 	dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - ctlr->seq);  in dm_pciauto_postscan_setup_bridge()
265 		dm_pci_write_config8(dev, 0x90, 0x20);  in dm_pciauto_postscan_setup_bridge()
271 		dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,  in dm_pciauto_postscan_setup_bridge()
278 		dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,  in dm_pciauto_postscan_setup_bridge()
285 		dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,  in dm_pciauto_postscan_setup_bridge()
289 			dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,  in dm_pciauto_postscan_setup_bridge()
292 			dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);  in dm_pciauto_postscan_setup_bridge()
300 		dm_pci_write_config8(dev, PCI_IO_LIMIT,  in dm_pciauto_postscan_setup_bridge()
302 		dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,  in dm_pciauto_postscan_setup_bridge()
311 int dm_pciauto_config_device(struct udevice *dev)  in dm_pciauto_config_device()  argument
316 	unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));  in dm_pciauto_config_device()
319 	struct udevice *ctlr = pci_get_controller(dev);  in dm_pciauto_config_device()
331 	dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);  in dm_pciauto_config_device()
336 		      PCI_DEV(dm_pci_get_bdf(dev)));  in dm_pciauto_config_device()
338 		dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io,  in dm_pciauto_config_device()
341 		n = dm_pci_hose_probe_bus(dev);  in dm_pciauto_config_device()
352 		dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io,  in dm_pciauto_config_device()
356 		      PCI_DEV(dm_pci_get_bdf(dev)));  in dm_pciauto_config_device()
363 		      PCI_DEV(dm_pci_get_bdf(dev)));  in dm_pciauto_config_device()
375 		dm_pciauto_setup_device(dev, 0, hose->pci_mem,  in dm_pciauto_config_device()
386 		dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io,  in dm_pciauto_config_device()