Lines Matching full:pcie
34 /* PCIe core registers */
102 /* PCIe core controller registers */
126 /* PCIe Retries & Timeout definitions */
135 * struct pcie_advk - Advk PCIe controller state
138 * @first_busno: This driver supports multiple PCIe controllers.
139 * first_busno stores the bus number of the PCIe root-port
140 * number which may vary depending on the PCIe setup
150 static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg) in advk_writel() argument
152 writel(val, pcie->base + reg); in advk_writel()
155 static inline uint advk_readl(struct pcie_advk *pcie, uint reg) in advk_readl() argument
157 return readl(pcie->base + reg); in advk_readl()
164 * @first_busno: Bus number of the PCIe controller root complex
171 * In PCIE-E only a single device (0) can exist in pcie_advk_addr_valid()
184 * @pcie: The PCI device to access
191 static int pcie_advk_wait_pio(struct pcie_advk *pcie) in pcie_advk_wait_pio() argument
197 start = advk_readl(pcie, PIO_START); in pcie_advk_wait_pio()
198 isr = advk_readl(pcie, PIO_ISR); in pcie_advk_wait_pio()
208 dev_err(pcie->dev, "config read/write timed out\n"); in pcie_advk_wait_pio()
215 * @pcie: Pointer to the PCI bus
220 static int pcie_advk_check_pio_status(struct pcie_advk *pcie, in pcie_advk_check_pio_status() argument
228 reg = advk_readl(pcie, PIO_STAT); in pcie_advk_check_pio_status()
240 *read_val = advk_readl(pcie, PIO_RD_DATA); in pcie_advk_check_pio_status()
278 dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n", in pcie_advk_check_pio_status()
280 advk_readl(pcie, PIO_ADDR_LS)); in pcie_advk_check_pio_status()
289 * @bdf: Identifies the PCIe device to access
304 struct pcie_advk *pcie = dev_get_priv(bus); in pcie_advk_read_config() local
308 dev_dbg(pcie->dev, "PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ", in pcie_advk_read_config()
311 if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) { in pcie_advk_read_config()
312 dev_dbg(pcie->dev, "- out of range\n"); in pcie_advk_read_config()
318 advk_writel(pcie, 0, PIO_START); in pcie_advk_read_config()
319 advk_writel(pcie, 1, PIO_ISR); in pcie_advk_read_config()
322 reg = advk_readl(pcie, PIO_CTRL); in pcie_advk_read_config()
324 if (PCI_BUS(bdf) == pcie->first_busno) in pcie_advk_read_config()
328 advk_writel(pcie, reg, PIO_CTRL); in pcie_advk_read_config()
332 advk_writel(pcie, reg, PIO_ADDR_LS); in pcie_advk_read_config()
333 advk_writel(pcie, 0, PIO_ADDR_MS); in pcie_advk_read_config()
336 advk_writel(pcie, 1, PIO_START); in pcie_advk_read_config()
338 if (!pcie_advk_wait_pio(pcie)) in pcie_advk_read_config()
342 ret = pcie_advk_check_pio_status(pcie, true, ®); in pcie_advk_read_config()
346 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n", in pcie_advk_read_config()
386 * @bdf: Identifies the PCIe device to access
401 struct pcie_advk *pcie = dev_get_priv(bus); in pcie_advk_write_config() local
404 dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ", in pcie_advk_write_config()
406 dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n", in pcie_advk_write_config()
409 if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) { in pcie_advk_write_config()
410 dev_dbg(pcie->dev, "- out of range\n"); in pcie_advk_write_config()
415 advk_writel(pcie, 0, PIO_START); in pcie_advk_write_config()
416 advk_writel(pcie, 1, PIO_ISR); in pcie_advk_write_config()
419 reg = advk_readl(pcie, PIO_CTRL); in pcie_advk_write_config()
421 if (PCI_BUS(bdf) == pcie->first_busno) in pcie_advk_write_config()
425 advk_writel(pcie, reg, PIO_CTRL); in pcie_advk_write_config()
429 advk_writel(pcie, reg, PIO_ADDR_LS); in pcie_advk_write_config()
430 advk_writel(pcie, 0, PIO_ADDR_MS); in pcie_advk_write_config()
431 dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg); in pcie_advk_write_config()
435 advk_writel(pcie, reg, PIO_WR_DATA); in pcie_advk_write_config()
436 dev_dbg(pcie->dev, "\tPIO req. - val = 0x%08x\n", reg); in pcie_advk_write_config()
440 advk_writel(pcie, reg, PIO_WR_DATA_STRB); in pcie_advk_write_config()
441 dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg); in pcie_advk_write_config()
444 advk_writel(pcie, 1, PIO_START); in pcie_advk_write_config()
446 if (!pcie_advk_wait_pio(pcie)) { in pcie_advk_write_config()
447 dev_dbg(pcie->dev, "- wait pio timeout\n"); in pcie_advk_write_config()
452 pcie_advk_check_pio_status(pcie, false, ®); in pcie_advk_write_config()
458 * pcie_advk_link_up() - Check if PCIe link is up or not
460 * @pcie: The PCI device to access
465 static int pcie_advk_link_up(struct pcie_advk *pcie) in pcie_advk_link_up() argument
469 val = advk_readl(pcie, CFG_REG); in pcie_advk_link_up()
477 * @pcie: The PCI device to access
484 static int pcie_advk_wait_for_link(struct pcie_advk *pcie) in pcie_advk_wait_for_link() argument
490 if (pcie_advk_link_up(pcie)) { in pcie_advk_wait_for_link()
491 printf("PCIE-%d: Link up\n", pcie->first_busno); in pcie_advk_wait_for_link()
498 printf("PCIE-%d: Link down\n", pcie->first_busno); in pcie_advk_wait_for_link()
504 * pcie_advk_setup_hw() - PCIe initailzation
506 * @pcie: The PCI device to access
510 static int pcie_advk_setup_hw(struct pcie_advk *pcie) in pcie_advk_setup_hw() argument
515 reg = advk_readl(pcie, CTRL_CONFIG_REG); in pcie_advk_setup_hw()
518 advk_writel(pcie, reg, CTRL_CONFIG_REG); in pcie_advk_setup_hw()
521 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in pcie_advk_setup_hw()
523 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in pcie_advk_setup_hw()
530 advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG); in pcie_advk_setup_hw()
532 /* Set PCIe Device Control and Status 1 PF0 register */ in pcie_advk_setup_hw()
535 advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG); in pcie_advk_setup_hw()
537 /* Program PCIe Control 2 to disable strict ordering */ in pcie_advk_setup_hw()
540 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in pcie_advk_setup_hw()
543 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in pcie_advk_setup_hw()
546 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in pcie_advk_setup_hw()
549 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in pcie_advk_setup_hw()
552 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in pcie_advk_setup_hw()
555 reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG); in pcie_advk_setup_hw()
557 advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG); in pcie_advk_setup_hw()
564 * the outbound transactions. Thus, PCIe address in pcie_advk_setup_hw()
567 reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG); in pcie_advk_setup_hw()
569 advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG); in pcie_advk_setup_hw()
577 reg = advk_readl(pcie, PIO_CTRL); in pcie_advk_setup_hw()
579 advk_writel(pcie, reg, PIO_CTRL); in pcie_advk_setup_hw()
582 reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG); in pcie_advk_setup_hw()
584 advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG); in pcie_advk_setup_hw()
586 /* Wait for PCIe link up */ in pcie_advk_setup_hw()
587 if (pcie_advk_wait_for_link(pcie)) in pcie_advk_setup_hw()
590 reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG); in pcie_advk_setup_hw()
594 advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG); in pcie_advk_setup_hw()
600 * pcie_advk_probe() - Probe the PCIe bus for active link
604 * Probe for an active link on the PCIe bus and configure the controller
611 struct pcie_advk *pcie = dev_get_priv(dev); in pcie_advk_probe() local
626 * The PCIe RESET signal is not supposed to be released along in pcie_advk_probe()
628 * possible before PCIe PHY initialization. Moreover, the PCIe in pcie_advk_probe()
632 dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n"); in pcie_advk_probe()
638 dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n"); in pcie_advk_probe()
641 pcie->first_busno = dev->seq; in pcie_advk_probe()
642 pcie->dev = pci_get_controller(dev); in pcie_advk_probe()
644 return pcie_advk_setup_hw(pcie); in pcie_advk_probe()
660 struct pcie_advk *pcie = dev_get_priv(dev); in pcie_advk_ofdata_to_platdata() local
663 pcie->base = (void *)dev_read_addr_index(dev, 0); in pcie_advk_ofdata_to_platdata()
664 if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE) in pcie_advk_ofdata_to_platdata()
676 { .compatible = "marvell,armada-37xx-pcie" },